Title:
METHOD OF FABRICATING A CHARGE-TRAPPING GATE STACK USING A CMOS PROCESS FLOW
Document Type and Number:
WIPO Patent Application WO/2015/119893
Kind Code:
A3
Abstract:
A method of fabricating a memory device is described. Generally, the method includes: forming on a surface of a substrate a dielectric stack including a tunneling dielectric and a charge-trapping layer overlying the tunneling dielectric; depositing a first cap layer comprising an oxide over the dielectric stack; forming a second cap layer comprising a nitride over the first cap layer; patterning the first and second cap layers and the dielectric stack to form a gate stack of a memory device; removing the second cap layer; and performing an oxidation process to form a blocking oxide over the charge-trapping layer, wherein the oxidation process consumes the first cap layer. Other embodiments are also described.
Inventors:
RAMKUMAR KRISHNASWAMY (US)
SHIH HUI MEI (TW)
SHIH HUI MEI (TW)
Application Number:
PCT/US2015/014118
Publication Date:
November 12, 2015
Filing Date:
February 02, 2015
Export Citation:
Assignee:
CYPRESS SEMICONDUCTOR CORP (US)
International Classes:
H01L29/423; H01L21/02; H01L21/28; H01L29/51
Foreign References:
| US20140264720A1 | 2014-09-18 | |||
| US20110215404A1 | 2011-09-08 | |||
| US6063706A | 2000-05-16 | |||
| US5942450A | 1999-08-24 | |||
| US5883010A | 1999-03-16 | |||
| US5293336A | 1994-03-08 |
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