Title:
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE AND EQUIPMENT FOR PROCESSING SUBSTRATE
Document Type and Number:
WIPO Patent Application WO/2006/137287
Kind Code:
A1
Abstract:
Throughput of a gate stack formation process is enhanced as a whole. When a gate stack formation process comprising a high dielectric film formation step, a plasma nitriding step, an anneal step, and a gate electrode formation step is performed on cluster equipment, the final gate electrode formation step is interrupted in the middle and the remaining gate electrode formation step is performed collectively for a plurality of sheets. Since the waiting time for a series of steps is shortened on the cluster equipment, throughput of the gate stack formation process is enhanced as a whole.
Inventors:
HORII SADAYOSHI (JP)
Application Number:
PCT/JP2006/311788
Publication Date:
December 28, 2006
Filing Date:
June 13, 2006
Export Citation:
Assignee:
HITACHI INT ELECTRIC INC (JP)
HORII SADAYOSHI (JP)
HORII SADAYOSHI (JP)
International Classes:
H01L21/02
Foreign References:
| JP2003229343A | 2003-08-15 | |||
| JPH11145021A | 1999-05-28 | |||
| JPH04322444A | 1992-11-12 | |||
| JPH0963915A | 1997-03-07 | |||
| JPH03196948A | 1991-08-28 |
Attorney, Agent or Firm:
Kajiwara, Tatuya (Central Nishi-Shinjuku 9-5, Nishi-Shinjuku 8-chom, Shinjuku-ku Tokyo 23, JP)
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