Title:
METHOD OF FORMING AND PATTERNING CONFORMAL INSULATION LAYER IN VIAS AND ETCHED STRUCTURES
Document Type and Number:
WIPO Patent Application WO/2011/104550
Kind Code:
A3
Abstract:
Vias are formed in a substrate using an etch process that forms an undercut profile below the mask layer. The vias are coated with a conformal insulating layer and an etch process is applied to the structures to remove the insulating layer from horizontal surfaces while leaving the insulating layers on the vertical sidewalls of the vias. The top regions of the vias are protected during the etchback process by the undercut hardmask.
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Inventors:
DITIZIO ROBERT (US)
Application Number:
PCT/GB2011/050361
Publication Date:
April 12, 2012
Filing Date:
February 24, 2011
Export Citation:
Assignee:
SPP PROCESS TECHNOLOGY SYSTEMS UK LTD (GB)
DITIZIO ROBERT (US)
DITIZIO ROBERT (US)
International Classes:
H01L21/768; B81B1/00; H01L21/02; H01L21/3065
Foreign References:
| US20060024966A1 | 2006-02-02 | |||
| US20070045858A1 | 2007-03-01 | |||
| US20070052067A1 | 2007-03-08 |
Other References:
GOBET J ET AL: "IC compatible fabrication of through-wafer conductive vias", PROCEEDINGS OF THE SPIE - THE INTERNATIONAL SOCIETY FOR OPTICAL ENGINEERING SPIE-INT. SOC. OPT. ENG. USA, vol. 3223, 1997, pages 17 - 25, XP002669296, ISSN: 0277-786X
MAJEED B ET AL: "Parylene N as a dielectric material for through silicon vias", 58TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE - 27-30 MAY 2008 20080527 IEEE, PISCATAWAY, NJ, USA, 27 May 2008 (2008-05-27), pages 1556 - 1561, XP031276403, ISBN: 978-1-4244-2230-2
MAJEED B ET AL: "Parylene N as a dielectric material for through silicon vias", 58TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE - 27-30 MAY 2008 20080527 IEEE, PISCATAWAY, NJ, USA, 27 May 2008 (2008-05-27), pages 1556 - 1561, XP031276403, ISBN: 978-1-4244-2230-2
Attorney, Agent or Firm:
DUNLOP, Brian et al. (Lainé & James LLPEssex Place,22 Rodney Road,Cheltenham, Gloucestershire GL50 1JJ, GB)
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