Title:
METHOD OF FORMING SHALLOW TRENCH ISOLATION IN SILICON
Document Type and Number:
WIPO Patent Application WO2002041393
Kind Code:
A3
Abstract:
A method of forming a shallow trench isolation region in a silicon wafer which results in the elimination of long range slip dislocations in the wafer and reduces leakage current across the isolation regions. Long shallow trenches (17) are formed in a silicon wafer (11) at a 45 degree angle to the (111) plane of the wafer. This is achieved by moving the primary flat of the wafer to the (100) plane prior to the formation of the trenches, which causes the bottom edges of the long trenches to intersect with several (111) planes, so that stresses do not propagate along any one single (111) plane. The trenches (17) are then filled with an insulative material, such as oxide.
Inventors:
MILLER ERIC R
MOON STEPHEN R
MOON STEPHEN R
Application Number:
PCT/US2001/042177
Publication Date:
August 29, 2002
Filing Date:
September 12, 2001
Export Citation:
Assignee:
ATMEL CORP (US)
International Classes:
H01L21/762; H01L21/76; (IPC1-7): H01L21/762
Foreign References:
| US6078078A | 2000-06-20 | |||
| US5576230A | 1996-11-19 |
Other References:
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 08 6 October 2000 (2000-10-06)
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