METHOD FOR FORMING WIRING

WIPO Patent Application WO/2014/057734

A1

The present invention addresses the problem of inhibiting the evolution of a poisoning gas to eliminate wiring-pattern resolution failures and thereby forming a desired wiring layer structure to provide functional elements having an improved property yield. This method for forming multilayered copper wiring on a semiconductor substrate comprises: forming a multilayer resist structure to form a given resist pattern on a substrate including an interlayer dielectric film that has via holes which have been formed in part thereof and filled with an SOC layer, the multilayer resist structure comprising an SOC layer, an SOG layer, an SiO2 layer, and a chemical amplification type resist superposed in this order from the substrate side; conducting etching using the resist pattern as a mask to form a pattern for a wiring layer and via plugs; and forming the wiring layer and the via plugs in the pattern.

WO/2011/046003	SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
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OKAMOTO KOICHIRO (JP)
TADA MUNEHIRO (JP)
HADA HIROMITSU (JP)
SAKAMOTO TOSHITSUGU (JP)

PCT/JP2013/072640

April 17, 2014

August 20, 2013

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NEC CORP (JP)

H01L21/768; H01L21/3065; H01L21/8246; H01L27/105; H01L43/08; H01L45/00; H01L49/00

JP2011091317A	2011-05-06
JP2007310086A	2007-11-29
JP2004172403A	2004-06-17
JP2004179393A	2004-06-24
JP2002222860A	2002-08-09
JP2006156998A	2006-06-15

IKEDA, Noriyasu et al. (JP)
Noriyasu Ikeda (JP)

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