The invention refers also to an apparatus that implements said method.

Although the invention is described for an application in an AXE10 system with network synchronisation, it can be applied to every system which requires a redundant unit for generating and distributing timing signals.

Clock and timing generation is the function providing to an exchange a high quality of timing signal ; network synchronisation make it possible for the exchange to be synchronized with other exchanges in the network.

Background of the invention Faced problem Generally, a system for generating and distributing timing signals based on two redundant units is strongly impaired whenever a fault occurrence produces a fast phase drift on clock/sync signals generated by one of the two clock units. When considering the system represented in Fig. 1 of the annexed drawings, it is to note that it is easy to immediately detect a loss of signals (fault 1), whilst the occurrence of a fault in VCXO control, which is the source of timing signals (fault 2) generates a phase drift which is not likely to be detected so fast. Although the timing user is able to do that, as soon as it switches onto the other timing input, a sudden phase jump occurs, which creates loss of synchronisation and disturbances on the traffic managed by the exchange. The extent of the phase jump depends on the time it takes the control system to find out the faulty unit and to exclude its output signals, so that the timing user can switch onto the other input. It is easy to understand that the phase jump can be sometimes very large.

Known solutions and their problems In the conventional AXE 10 system the above problem is solved by triplicating the unit for generating and distributing the clock and by positioning a circuit for

preferential routing at the input of the timing user, as it is shown in Fig. 2 of the annexed drawings.

Triplicating clock unit allows to fast detect a possible phase drift in each of the oscillators included in the clock system and the circuit for preferential routing masks every possible phase drift. The output of the circuit for preferential routing can generate spikes if the three units are not perfectly aligned and one of the oscillators starts to drift, but these spikes can be easily filtered by the timing user. The loss can still be detected by detectors of signal presence.

Conventional solution solves the above problems, but exhibits a few disadvantages. Additional clock unit and cables (as many cables as the timing users, namely for 16 timing users 16 additional cables) are to be added, so increasing hardware bulk and cost.

Control and supervision of the circuit for preferential routing, which is functionally part of the system for generating and distributing the clock, are to be done by the timing user, since it is physically positioned there. This is a problem, since this solution complicates software design as for fault isolation and continuous supervision.

Summary of the invention This invention aims at keeping the advantages of the conventional AXE10 solution which has already been described, while avoiding its disadvantages, and, for this purpose, it refers to a method and a redundant apparatus for generating and distributing timing, which utilise a duplicated clock unit.

The inventive method comprises the steps of: - promptly detecting any phase drift occurring in oscillators ; - masking any phase drift, so that it is not visible at the input of any timing user; and - eluding any possible phase jump, thus avoiding disturbances on the traffic managed by the exchange.

The redundant, inventive apparatus for generating and distributing timing signals, which implements such a method, is in turn characterised in that it comprises two units for generating timing signals, each of them being provided with two VCXO oscillators, controlled by two separated PLL (Phase locked loop) circuits

and in that one of the two units operates in it as a master unit and the other one as a slave unit.

Brief description of the drawings The invention is now depicted more in depth, referring to the annexed drawings, wherein: Fig. 1 shows a conventional, duplicated system for timing generation, connected to timing users; Fig. 2 shows a conventional AXE10 system for timing generation and the configuration scheme of the distribution to timing users; and Fig. 3 shows the inventive system for generating timing.

Description of a preferred embodiment As shown in Fig. 3 of the annexed drawings, the inventive apparatus implementing the above method and that can ensure the above reported features, comprises two units 10 and 20 for generating timing signals, said units being identical, each of them being provided with two oscillators VCXO_A and VCXO_B, controlled by two separated PLL circuits. The PLL circuits have the purpose to perfectly keep phase aligned all of the four oscillators, so that they operate as a single logical oscillator.

The system operates according to the hierarchy master/slave, that is a unit is chosen as a master, whilst the other one operates as a slave. Thus, whenever a clock unit is chosen as a master, its VCXO_A either regulates towards a signal provided from outside to synchronise the network, or is kept in hold over while its VCXOB regulates towards VCXO_A. In the clock unit chosen as a slave, both VCXO_A and VCXO_B regulate towards the VCXOA of the master unit. In this way, the phase difference among the four oscillator is kept as equal to zero as possible. The PLL circuits are digitally controlled, so that their bandwidth is wide enough so that it can track small frequency changes in the master oscillator, but also narrow enough so that the oscillator of the slave does not track a fast drift of the master. Thus, even a phase drift of the master can be isolated. The phase difference among the four oscillators is subject to a continuous supervision, according to the following Table : Table 1-Phase difference supervision concept

#A0A1 #A0B0 #A0B1 #A1B0 #A1B1 Unit to be blocked Unit 0 l Unit 1 unit 0 unit 1 All other cases Unit reporting the fault wherein ticked cells show a phase drift over the admitted limit and wherein DAOA1 is the phase difference between the VCXOA of unit 10 and the VCXO A of unit 20.

In each unit both phase meters can measure the phase difference among the four oscillators and the value measured by one can be compared to the value measured by the other one, in order to avoid that a fault in a phase meter can affect both oscillators in a unit. In order to improve the robustness with respect to a single fault, PLL circuits are as separated as possible, namely they are implemented in two separated circuits.

The function of preferential routing is performed according to the following table : Table 2-Operation of Majority vote UNIT NUMBER, SIGNAL A SiGNAL B I SIGNAL C UNIT_0 VCXO A VCXO_B VCXO A from UN) T1 UNIT_1 VCXO_A VCXO_B VCXO A from UNI 0 Information given by this table can be found also in Fig. 3. It is worth noting that inputs for preferential routing are not the same, but output signals are the same, because the four oscillators have the same phase. As it is set forth above, the preferential routing masks any phase drift until the control system excludes timing signals outgoing from the faulty unit, thus preventing phase jumps on input of timing user.

The system structure, with respect to the presently existing AXE10, lowers hardware costs, because a hardware unit and a number of cables can be saved.

Furthermore, it simplifies software design, since the supervision of the whole function of clock generation is performed by the clock unit.

Finally, it is easier to operate with the clock system, since the number of units is lowered by one.

Changes and modifications of this invention will be apparent to skilled persons, while, although the invention has been described for an application in an AXE10 system, its application to any system requiring a redundant unit for generating and distributing timing is conceivable.