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Title:
METHOD FOR IMPROVEMENT OF SLEW RATE IN ANALOG DRIVER CIRCUITS
Document Type and Number:
WIPO Patent Application WO/2022/216265
Kind Code:
A1
Abstract:
Invention relates to a method that enables driving of high capacitance loads with low power consumption by means of momentarily changing currents of current sources that determines currents of output transistors of the amplifier according to the change direction of input signals.

Inventors:
KELLECİ BURAK (TR)
İNCETÜRKMEN ERCIHAN (TR)
Application Number:
PCT/TR2022/050312
Publication Date:
October 13, 2022
Filing Date:
April 08, 2022
Export Citation:
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Assignee:
ASELSAN ELEKTRONIK SANAYI VE TICARET AS (TR)
International Classes:
H03F1/02; H03F3/45
Foreign References:
US20170086269A12017-03-23
US6359512B12002-03-19
US20030090321A12003-05-15
Other References:
ZHAO XIAO ET AL: "Transconductance and slew rate improvement technique for current recycling folded cascode amplifier", AEU - INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS, ELSEVIER, AMSTERDAM, NL, vol. 70, no. 3, 23 December 2015 (2015-12-23), pages 326 - 330, XP029388411, ISSN: 1434-8411, DOI: 10.1016/J.AEUE.2015.12.015
ANONYMOUS: "Capacitive coupling - Wikipedia", 26 December 2020 (2020-12-26), pages 1 - 3, XP055956575, Retrieved from the Internet [retrieved on 20220831]
Attorney, Agent or Firm:
DESTEK PATENT, INC. (TR)
Download PDF:
Claims:
CLAIMS

1. A method for improving slew rate in analog drive circuits characterized by comprising process steps of

• Detecting circuit input change by use of input signal-1 (Vinp), o In the case where input signal-1 (Vinp) increases,

Increase of the output level to supply potential by electronic amplifier-1 (1),

Applying change in output value of electronic amplifier-1 to transistor-10 (M10) via capacitor-1 (C1) connected to electronic amplifier-1 (1),

Decrease of the output level of electronic amplifier-2(2) from supply potential to ground potential,

Applying change in the output value of electronic amplifier-2 (2) to transistor-11 (M11) via capacitor-2 (C2) connected to electronic amplifier-2 (2),

Increasing current of transistor-10 (M10) subject to change and increasing current flowing to output upon decrease in current of transistor- 11 (M11), o In the case where input signal-1 (¾ ¥j decreases,

Decrease of the output level of electronic amplifier-1 (1) from supply potential to ground potential,

Applying change in output value of electronic amplifier-1 to transistor-10 (M10) via capacitor-1 (C1) connected to electronic amplifier-1 (1),

Decrease of output level of electronic amplifier-2 (2) from ground potential to supply potential, Applying change in output value of electronic amplifier-2 (2) to transistor- 11(M11) via capacitor-2 (C2) connected to electronic amplifier-2 (2),

Decreasing current of transistor-10 (M10) subject to change and decreasing current flowing to output upon decrease in current of transistor- 11 (M11),

Description:
Method for improvement of Slew Rate in Analog Driver Circuits

The Field of the Invention

The invention relates to a method for driving of high capacitance load in analog driver circuits using low power consumption.

Invention particularly relates to a method for driving of high capacitance loads by consuming low power by changing currents of current sources which determines currents of output transistors of amplifier in operation instantly according to the change of input signals.

Background of the Invention

The output stages of amplifiers consume high current in order to drive high capacitance loads quickly. When high speed driving is required, either the current of the circuit is increased or extra current is supplied to or taken from the output by a parallel circuit.

If the current of circuit is increased to drive high capacitance loads at high speed, the power consumption of the circuit is increased. In addition, if a circuit is used to supply extra current to output, undesired parasitic capacitance increase occurs at the output node.

The closest prior art is believed to include commonly assigned U.S. Patent No. 5070307 entitled “Differential Amplifier with Enhanced Slew Rate” which relates to differential amplifiers having improved slew rate. The application discloses output current is increased to charge output capacitance quickly if high output is required. If low output is required, the controllable current source drains output current to discharge output capacitance quickly. The application numbered US5070307 is convenient for fully differential signal case. In addition, application numbered US5070307 uses 2 differential amplifiers for push-pull structure. Since our application uses 2 pieces of single stage amplifiers, it has less complicated structure. The adjustment in embodiment disclosed under our application is only made during input signal changes. Whereas adjustment is continuously made in application numbered US5070307.

As a result, due to above described disadvantages and inadequacy of existing solutions it has been necessary to make development in the related technical field. Purpose of the Invention

The invention has been developed with inspiration from existing situation and aims to eliminate the above-mentioned disadvantages.

Purpose of the invention is to drive high capacitance loads with low current consumption by momentarily changing the output current.

Another purpose of the invention is to prevent addition of extra parasitic capacitance at output by not directly intervening output node.

Another purpose of the invention is to eliminate need for extra structure by intervening currents of current sources available in the circuit. The structural and characteristics features of the invention and all advantages will be understood better in detailed descriptions with the figures given below and with reference to these figures, and therefore, the assessment should be made taking into account the figures and detailed explanations.

Description of Figures Figure 1 is a circuit diagram of amplifier of the related art.

Figure 2 is a circuit diagram of amplifier of the invention.

Description of Part References

1 . Electronic amplifier-1

2. Electronic amplifier-2 M1 , M2,.. ,M11.Transistor-1 , Transistor-2,..., Transistor- 11

R1 Resistor-1 R2. Resistor-2 C1. Capacitor -1

C2. Capacitor -2 C out Output Capacitor

V inp Input signal-1 .V inm Input signal-2

V bni : Voltage value that determines the gate voltages of Transistor-8 (M8) and Transistor-9 (M9)

V bn2 : Voltage value that determines the current value of transistors when there is no signal at amplifier input

V pi : Voltage value that determines the gate voltage of Transistor-3 (M3)

V p 2 ; Voltage value that determines the gate voltages of Transistor-6 (M6) and Transistor-7 (M7)

V out : Output signal

Detailed Description of the Invention

In this detailed description, the preferred embodiments of the invention have been described in a manner not forming any restrictive effect and only for purpose of better understanding of the matter.

Amplifier circuit shown in Figure 1 amplifies differential values of signals applied to input signal-1 (V inp ) and input signal-2 (V inm ), and applies to its output. If input signal -1 (V inp ) is at a more positive voltage level than input signal-2 (V inm ), most of transistor-3 (M3) current is flown through transistor-1. In this case, since transistor-11 (M11 ) current is fixed current, the current of transistor-9 (M9) decreases. As the current of transistor-2 (M2) decreases, most of the current of transistor-10 (M10) flows through transistor-8 (M8). Since the current of transistor-8 (M8) is transferred to the output node by active current mirror formed by transistor-4 - transistor-7 (M4-M7), current flowing to output increases and the voltage of the output node increases. If the input signal-1 (Vinp) has a more negative voltage level than the input signal-2 (Vinm), the current of transistor-8 (M8) decreases, so the current applied to output node by current mirror of transistor-4- transistor-7 (M4-M7) decreases. As the current flowing through transistor-1 (M1) decreases, the current of transistor-11 (M11) flows through transistor-9 (M9) and decreases output node voltage. Since transistor-10 (M10) and transistor-11 (M11) are current sources, their current is independent of signal level and changes. In this case, output current used for increasing or decreasing the output voltage decreases and periods of increasing and decreasing of output signal get longer.

In the method of the invention shown in Figure 2, currents of transistor-10 (M10) and transistor-11 (M11) are changed for short time according to the change direction of the input signal. Since input signal-(2) (V inm ) is also used for feedback, the change of input is detected by using of input signal-1 (V inp ) in order not to change feedback characteristics of the circuit. Electronic amplifier-1 (1) and electronic amplifier-2 (2) amplify input signal so that their outputs are changed between ground and supply level.

Method of the invention fundamentally comprises following process steps;

Detecting circuit input change by use of input signal-1 ( V inp ) ,

• Amplification of input signal-1 ( V inp ) by electronic amplifiers and switching output values between ground and supply levels, o In the case where input signal-1 ( V inp ) increases,

Increase of output level to supply potential by electronic amplifier-

1 (1),

Applying change in output value of electronic amplifier-1 to transistor-10(M10) via capacitor-1 (C1) connected to electronic amplifier-1 (1),

Increasing the current of transistor-10 (M10) subject to change and increasing current flowing to the output via transistor-4 transistor-7 (M4-M7) current mirror,

Decrease of output level of electronic amplifier-2(2) from supply potential to ground potential, Applying change in output value of electronic amplifier-2 (2) to transistor- 11(M11) via capacitor-2 (C2) connected to electronic amplifier-2 (2),

Thus, as the current of transistor-11 (M11) decreases, the current taken by transistor-11 (M11) from the output node decreases. Since current flowing to the output load increases, the voltage of the output node reaches to desired value quickly. o In the case where input signal-1 (V inp ) decreases,

Decrease of output level of electronic amplifier-1 (1) from supply potential to ground potential,

Applying change in output value of electronic amplifier-1 to transistor-10(M10) via capacitor-1 (C1) connected to electronic amplifier-1 (1),

Decreasing the current of transistor-10 (M10) subject to change and decreasing current flowing to the output node via transistor-4 transistor-7 (M4-M7) current mirror,

Decrease of the output level of electronic amplifier-2(2) from ground potential to supply potential,

Applying change in output value of electronic amplifier-2 (2) to transistor- 11(M11) via capacitor-2 (C2) connected to electronic amplifier-2 (2),

Thus, as the current of transistor-11 (M11) increases, the current taken by transistor-11 (M11) from the output node increases. Since the current drawn from the output load increases, the voltage of the output node reaches to desired value quickly.

In order for currents of transistor-10 (M10) and transistor-11 (M11) to be determined by V bn2 in the absence of signal change, the gate of transistor-10(M10) is connected via resistance-1(R1) to V bn2 potential and the gate of transistor-11 (M11) is connected via resistance-2 (R2) V bn2 potential. Capacitor-1 (C1) and resistor (R1) function as high pass filter and apply signal change at the output of electronic amplifier-1 (1) to gate of transistor-10 (M10). Voltage value of the gate of Transistor- 10 (M 10) returns to value of V bn2 according to R1C1 time constant. Since R1C1 time constant is selected less than one read period, the gate voltage value of transistor-10 (M10) becomes V bn2 when reading the output voltage value.

Similarly, capacitor-2 (C2) and resistance-2 (R2) work as filter of high filtering. Signal change at output of electronic amplifier-2 (2) is applied to the gate of transistor-11 (M11) and the gate voltage of transistor-11 (M11) changes momentarily. The gate voltage of Transistor-11 (M11) returns to the value of V bn2 according to R2C2 time constant. Since R2C2 time constant is selected less than one read period, the gate voltage value of transistor-11 (M11) becomes V bn2 when reading the output voltage value,