Title:
METHOD OF IMPROVING AMPLIFIER INPUT OFFSET, AND AMPLIFIER
Document Type and Number:
WIPO Patent Application WO/2000/057546
Kind Code:
A1
Abstract:
A small-signal amplifier of low current consumption and small circuit scale, whose input offset is improved. The amplifier comprises an amplifier circuit that includes a first input for receiving an input signal and a second input for receiving a reference voltage, an up/down counter, and a D/A converter for converting the count of the up/down counter to a corresponding analog value. The output of the D/A converter is the reference voltage. The amplifier further comprises an offset comparator for comparing the reference voltage from the amplifier circuit with the output voltage to produce the difference signal, and a counter control section that generates an increment signal for incrementing the up/down counter according to the output from the offset comparator. An ROM control section generates an increment signal for controlling the increment of the up/down counter so that the output of the offset comparator may become zero.
Inventors:
SHIMIZU KAZUYOSHI (JP)
Application Number:
PCT/JP1999/001371
Publication Date:
September 28, 2000
Filing Date:
March 19, 1999
Export Citation:
Assignee:
FUJITSU LTD (JP)
SHIMIZU KAZUYOSHI (JP)
SHIMIZU KAZUYOSHI (JP)
International Classes:
H03F1/30; H03F3/21; (IPC1-7): H03F3/34; H03F3/08; H03F3/45; H03F3/68; H04B10/06
Foreign References:
| JPH03114065U | 1991-11-22 | |||
| JPH04111608A | 1992-04-13 | |||
| JPH05343931A | 1993-12-24 | |||
| JPH08223228A | 1996-08-30 | |||
| JPH06310967A | 1994-11-04 | |||
| JPH0372704A | 1991-03-27 |
Attorney, Agent or Firm:
Hayashi, Tsunenori (Doi & Associates Toshou-Building No.3
3-9-5 Shin-yokohama Kohoku-ku, Yokohama-shi Kanagawa, JP)
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