METHOD FOR INSPECTING ACTIVE MATRIX SUBSTRATE

WIPO Patent Application WO/2012/056497

A1

Disclosed is a method for inspecting an active matrix substrate, which is provided with a scanning line (12), a data line (11), light emitting pixels (1a) in matrix, and a power supply line (19). Each of the light emitting pixels (1a) is provided with: an organic EL element (13); a drive transistor (14); a capacitor (15); selective transistors (16, 17), each of which has the gate thereof connected to the scanning line (12), and is connected to between the data line (11) and the gate of the drive transistor (14); and a transistor (18) for guard potential, said transistor having the gate thereof connected to the source of the selective transistor (16), the source thereof connected to the drain of the selective transistor (16), and a power supply line (19) thereof connected to the drain. The inspection method includes: a write step (S11) of writing a charge in the capacitor (15); a readout step (S13) of reading out the written charge from the capacitor (15); and a holding step (S12) of holding the written charge for a predetermined period from the completion of the write step (S11) to the start of the readout step (S13).

TAJIKA KENICHI
SHIROUZU HIROSHI

PCT/JP2010/006371

May 03, 2012

October 28, 2010

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PANASONIC CORP (JP)
TAJIKA KENICHI
SHIROUZU HIROSHI

G09G3/30; G09F9/30; G09G3/20; H01L27/32; H01L51/50; H05B33/12

JPH05142573A	1993-06-11
JP2008070702A	2008-03-27
JPH1062817A	1998-03-06
JP2000010072A	2000-01-14
JP2001194646A	2001-07-19
JP2009086252A	2009-04-23
JP2005202070A	2005-07-28
JP2003337546A	2003-11-28

NII, Hiromori (JP)
New house Extensive 守 (JP)

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