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Title:
METHOD FOR KEEPING PHASES OF FREQUENCY DIVISION CLOCKS CONSISTENT AND FREQUENCY DIVISION CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2017/121228
Kind Code:
A1
Abstract:
A method for keeping phases of frequency division clocks consistent and a frequency division circuit. The method comprises: connecting an input end D of a last-level register of a first frequency divider with an input end D of a last-level register of a second frequency divider, wherein the first frequency divider is located outside a curing module, and the second frequency divider is located inside the curing module (201); and the first frequency divider and the second frequency divider respectively performing frequency division on a source clock signal, outputting a first frequency division signal at an output end Q of the last-level register of the first frequency divider, and outputting a second frequency division signal at an output end Q of the last-level register of the second frequency divider, wherein the phase of the first frequency division signal is consistent with the phase of the second frequency division signal (202).

Inventors:
SUN, Huayi (ZTE Industrial Park, Liuxian Avenue Xili Street, Nanshan Distric, Shenzhen Guangdong 5, 518055, CN)
Application Number:
CN2016/110952
Publication Date:
July 20, 2017
Filing Date:
December 20, 2016
Export Citation:
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Assignee:
SANECHIPS TECHNOLOGY CO., LTD. (ZTE Industrial Park, Liuxian Avenue Xili Street, Nanshan Distric, Shenzhen Guangdong 5, 518055, CN)
International Classes:
H03K23/00
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (2nd Floor, Zhongguancun Intellectual Property Building Block B, No.21 Haidian South Road, Haidian, Beijing 0, 100080, CN)
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