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Title:
METHOD FOR MACHINING NITRIDE SEMICONDUCTOR WAFER, NITRIDE SEMICONDUCTOR WAFER, PROCESS FOR PRODUCING NITRIDE SEMICONDUCTOR DEVICE, AND NITRIDE SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2009/107567
Kind Code:
A1
Abstract:
Disclosed is a method for machining a nitride semiconductor wafer that, when a nitride semiconductor crystal is subjected to back grinding, outer periphery grinding (chamfer), and surface grinding/polishing to produce a mirror wafer, causes no significant warpage, is free from cracking, and can realize a high substrate production process yield, and a high device in-plane yield. The outer peripheral part of a nitride semiconductor wafer is chamfered with a rubber grinding stone or a resin foam bonded grinding stone comprising 0 to 40% by weight of oxide abrasive grains to allow a work affected layer having a thickness of 0.5 μm to 10 μm to stay on the outer peripheral part.

Inventors:
ISHIBASHI KEIJI (JP)
MIKAMI HIDENORI (JP)
MATSUMOTO NAOKI (JP)
Application Number:
PCT/JP2009/053112
Publication Date:
September 03, 2009
Filing Date:
February 16, 2009
Export Citation:
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Assignee:
SUMITOMO ELECTRIC INDUSTRIES (JP)
ISHIBASHI KEIJI (JP)
MIKAMI HIDENORI (JP)
MATSUMOTO NAOKI (JP)
International Classes:
H01L21/304; B24B9/00; B24D3/00; B24D3/22; B24D3/32; H01L21/306; H01L21/3065; H01L33/32
Domestic Patent References:
WO2007018074A12007-02-15
Foreign References:
JPH09168947A1997-06-30
JP2005136311A2005-05-26
JP2005136167A2005-05-26
JP2008028259A2008-02-07
JP2007042748A2007-02-15
JPS63150158A1988-06-22
JPS63144966A1988-06-17
JP2001138244A2001-05-22
JP2006043884A2006-02-16
JP2004158537A2004-06-03
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JP2000265160A2000-09-26
JP2003510418A2003-03-18
JP2007223004A2007-09-06
JP2007254258A2007-10-04
JP2006203058A2006-08-03
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JP2005136167A2005-05-26
JP2004319951A2004-11-11
JP2003275935A2003-09-30
Other References:
See also references of EP 2246877A4
Attorney, Agent or Firm:
KAWASE, Shigeki (La Vida Nishinomiya 170412-33, Ikeda-cho,Nishinomiya-cit, Hyogo 11, JP)
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