INSULATOR SUBSTRATE

RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No.

62/238,638 filed October 7, 2015, and which is incorporated herein by reference.

FIELD OF THE INVENTION

[0002] The present invention relates to embedded non-volatile memory devices.

BACKGROUND OF THE INVENTION

[0003] Non-volatile memory devices formed on bulk silicon semiconductor substrates are well known. For example, U.S. Patents 6,747310, 7,868,375 and 7,927,994 disclose memory cells with four gates (floating gate, control gate, select gate and erase gate) formed on a bulk semiconductor substrate. Source and drain regions are formed as diffusion implant regions into the substrate, defining a channel region therebetween in the substrate. The floating gate is disposed over and controls a first portion of the channel region, the select gate is disposed over and controls a second portion of the channel region, the control gate is disposed over the floating gate, and the erase gate is disposed over the source region. Bulk substrates are ideal for these type of memory devices because deep diffusions into the substrate can be used for forming the source and drain region junctions. These three patents are incorporated herein by reference for all purposes.

[0004] Silicon on insulator (SOI) devices are well known in the art of microelectronics. SOI devices differ from bulk silicon substrate devices in that the substrate is layered with an embedded insulating layer under the silicon surface (i.e. silicon-insulator- silicon) instead of being solid silicon. With SOI devices, the silicon junctions are formed in a thin silicon layer disposed over the electrical insulator that is embedded in the silicon substrate. The insulator is typically silicon dioxide (oxide). This substrate configuration reduces parasitic device capacitance, thereby improving performance. SOI substrates can be manufactured by SEVIOX (separation by implantation of oxygen using an oxygen ion beam implantation - see U.S. Patents 5,888,297 and 5,061,642), wafer bonding (bonding oxidized silicon with a second substrate and removing most of the second substrate - see U.S. Patent 4,771,016), or seeding (topmost silicon layer grown directly on the insulator - see U.S. Patent 5,417,180). These four patents are incorporated herein by reference for all purposes.

[0005] It is known to form core logic devices, high voltage devices, input/output and/or analog devices on the same silicon substrate as non-volatile memory devices (i.e. typically referred to as embedded memory devices). As device geometries continue to shrink, core logic devices could benefit greatly from the advantages of SOI substrates. However, the non- volatile memory devices are not conducive to SOI substrates. There is a need to combine the advantages of core logic devices formed on an SOI substrate with memory devices formed on silicon bulk substrates.

BRIEF SUMMARY OF THE INVENTION

[0006] The aforementioned problems and needs are addressed by a method of forming a semiconductor device that includes providing a substrate that includes silicon, a first insulation layer directly over the silicon, and a silicon layer directly over the first insulation layer, epitaxially growing silicon on the silicon layer in a first area of the substrate and not in a second area of the substrate such that the silicon layer is thicker in the first area of the substrate relative to the second area of the substrate, forming memory cells in the first area of the substrate and forming logic devices in the second area of the substrate. The forming of each of the memory cells includes forming spaced apart first source and first drain regions in the silicon layer in the first area of the substrate, defining a channel region there between, forming a floating gate over and insulated from a first portion of the channel region, and forming a select gate over and insulated from a second portion of the channel region.

Forming of each of the logic devices includes forming spaced apart second source and second drain regions the silicon layer in the second area of the substrate, and forming a conductive gate over and insulated from a portion of the silicon layer between the second source and second drain regions. [0007] Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figs. 1-9, 15, 17, 19 and 21 are side cross sectional views of the logic area and memory area illustrating in sequence the processing steps performed to manufacture the embedded memory device of the present invention.

[0009] Figs. 10, 12, 14 and 16 are side cross sectional views, orthogonal to those of Figs. 9, 11, 13, and 15 respectively, of the memory area illustrating the next processing steps performed to manufacture the embedded memory device of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0010] The present invention is an embedded memory device with non- volatile memory cells formed alongside logic devices on an SOI substrate. The silicon on the insulator is raised (i.e. enhanced in thickness) in just the memory array area, while the logic device remain formed on a thin silicon layer of the SOI substrate. The raised silicon allows for the formation of a floating gate oxide by using thermal oxidation, CVD, or combination of both, because thermal oxidation will oxidize silicon and make it thinner. The raised silicon also allows for the formation of a Source Line (SL) junction deep enough to sustain a higher breakdown voltage compared to that for the logic N+ junction. The SL junction will be deeper than logic N+ junction due to thicker silicon and higher HVII implant energy.

[0011] The process of forming embedded memory devices on an SOI substrate begins by providing an SOI substrate 10, as illustrated in Fig. 1. The SOI substrate includes three portions: underlying (bulk) silicon 12, a layer of insulating material 14 (e.g. oxide - referred to as buried oxide - BOX) over the bulk silicon 12, and a thin layer of silicon (Si) 16 over the insulator BOX layer 14. Forming SOI substrates is well known in the art as described above and in the U.S. patents identified above, and therefore is not further described herein. [0012] An oxide layer 18 (Pad Ox) is formed on the thin silicon layer 16, and a nitride layer 20 (pad nitride) is deposited on the oxide layer 18, as shown in Fig. 2. A

photolithography process is performed which includes forming a photo-resist material on the nitride layer 20, followed by selectively exposing the photo-resist material to light using an optical mask, which is followed by selectively removing portions of the photo-resist material to expose portions of the underlying material (i.e., the nitride layer 20). Photolithography is well known in the art. A series of nitride, oxide, and silicon anisotropic etches are then performed in those portions left exposed by the photo resist to remove exposed portion of nitride 20, oxide 18, thin silicon 16, insulation 14 and bulk silicon 12, forming trenches 22 that extend through these layers and into the SOI substrate 10. An additional nitride etch

(e.g. isotropic) is performed to pull back the edges of the nitride layer 20 relative to the layers underneath by a specific pull-back amount (e.g. 40 to 100 angstroms) to widen the trenches 22 at the nitride layer 20 but not at the oxide 18. The resulting structure is shown in Fig. 3 (after photo resist removal). The spacing, width and orientation of the trenches 22 varies between the memory area 24 of the substrate 10 (in which memory cells will be formed) and the logic area 26 of the substrate 10 (in which logic devices will be formed).

[0013] The trenches 22 are then filled with an insulating material 28 such as CVD oxide (e.g., HDP oxide - High Density Plasma, or HARP oxide - High-Aspect-Ratio Process) by an oxide deposition and oxide etch (e.g. chemical mechanical polish - CMP - using the nitride 20 as an etch stop). Preferably, a recess etch is used to lower the tops of the STI oxide 28 below the top of the nitride layer 20, resulting in the structure shown in Fig. 4. This STI insulating material serves as isolation regions for both the logic area 26 and memory area 24.

[0014] A nitride etch is next performed to remove the nitride layer 20, leaving second trenches 30 between the pillars of STI oxide 28, as illustrated in Fig. 5. A layer of insulation material 32 (e.g. nitride - Cap Nitride) is formed over exposed surfaces of the structure by, for example, nitride deposition. A photolithography process is performed to form photoresist over the structure, followed by a masking step in which the photo resist is removed from the memory area 24 but not the logic area 26 of the structure. A nitride etch is performed to remove nitride layer 32 from the memory area 24, as shown in Fig. 6 (after photoresist removal). An oxide etch is performed to remove the oxide layer 18 at the bottoms of the second trenches in memory area. The oxide etch also may reduce the height of STI oxide 28 in the memory area 24. Oxide layer 18 is protected by nitride layer 32 in the logic device area 26 and maintained. Silicon is then epitaxially grown on the exposed thin silicon layer 16 at the bottoms of second trenches 30 in the memory area 24 to obtain a thicker silicon layer 16a, as shown in Fig. 7. This silicon epitaxial growth effectively increases the thickness of the silicon layer 16a over the BOX layer 14 in the memory area 24, without affecting the thickness of the silicon layer 16 over the BOX layer 14 in the logic area 26. [0015] An oxide formation step (e.g. oxidation) is then used to form an oxide layer (FG Ox) 34 on the thickened silicon layer 16a in the memory area 24 (which is the oxide on which the memory cell floating gates will be formed). Poly silicon is formed over the structure, followed by a poly etching (e.g. CMP), leaving a poly layer 36 in the second trenches (between STI oxide stacks 28) in both the logic area 26 and the memory area 24. A photolithography masking step is used to cover the memory area 24 only, so that a poly etch can be performed to reduce the height of the poly layer 36 in the logic area 26, and so that thicknesses of the poly layer 36 in the memory area 24 and the logic area 36 are

approximately equal, as shown in Fig. 8 (after photoresist removal). This allows for subsequent poly etching in both the memory area and the logic area to be done at the same time. This step could be skipped if the poly layer thicknesses are already about the same after poly etching (e.g., CMP).

[0016] A series of processing steps are next performed to complete the memory cell formation in the memory area 24, which are well known in the art. Specifically, the poly silicon 36 in the memory area 24 forms the memory cell floating gates. An optional oxide etch can be used to lower the tops of STI oxide 28 in the memory area 24. Memory stack structures are formed starting with forming a composite insulating layer (e.g.

oxide/nitride/oxide - ONO) 38 over the polysilicon 36 and STI oxide 28. A conductive control gate CG 40 (e.g. polysilicon) is formed on the composite insulating layer 38 in the memory area 24 and over the FG poly 36, and a hard mask material 42 (CG Hard Mask, such as nitride or a composite layer of nitride, oxide and nitride) is formed over the control gate 40. The CG hard mask 42, control gate poly 40, ONO insulation 38 and FG poly 36 are removed from the logic area 26 during the memory cell stack etching. A tunnel oxide layer 44 is then formed in both the memory area 24 and the logic area 26 (by CVD deposition). Figs. 9 and 10 show the resulting structure (Fig. 10 is a view orthogonal to that of Fig. 9 showing memory cells being formed in the memory area 24).

[0017] A source junction SL 46 is formed (e.g. implanted) in the thickness enhanced silicon layer 16a of the memory area 24 between adjacent floating gates (FG Poly) 36 (e.g. using patterned photo resist to prevent implantation in other exposed areas of the substrate 10). Photo resist 48 is then formed partially covering pairs of memory cells (by

photolithographic exposure and selective removal of the photo resist). Oxide and nitride etches are then performed to remove portions of oxide layers 18 and 44 and nitride layer 32 not protected by photo resist, exposing the thin silicon layer 16 of the logic area 26 of the SOI substrate 10. Spacers of oxide layer 44 remain along the sidewalls of floating gate 36, control gate 40 and hard mask 42. Figs. 11 and 12 show the resulting structures.

[0018] After removal of photo resist 48, an insulation layer 50 (e.g. oxide) is then formed on the exposed silicon 16 in logic area 26 and the exposed silicon 16a in the memory area 24, by for example thermal oxidation. A layer of polysilicon is then deposited and etched back to form erase gates EG 52 over source regions 46, word line (select) gates 54 on the other sides of floating gates 36 in the memory area 24, and logic gates 56 in the logic area 26 (using photolithography patterning and etch processes). Preferably, these poly gates are formed as follows. First, a layer of polysilicon is deposited over the structure. A protective insulator such as oxide is deposited on the polysilicon. The protective oxide is removed in the memory area 24 but not in the logic area 26 using photolithographic and oxide etch processes. Dummy polysilicon is then deposited over the structure. Poly CMP and etch back processes are used to form the gate poly 52/54 in the memory area 24. The protective oxide in the logic area 26 prevents the poly etch and etch back processes from affecting the polysilicon in the logic region 26 (once the dummy polysilicon is removed). Then, photolithographic and etch processes are used to pattern the polysilicon in the logic area 26 to form the logic gates 56, and to complete forming the WL gates 54 in the memory area 24. The resulting structure is shown in Figs. 13 and 14.

[0019] An LLD implant into the substrate 10 is next performed, which is followed by the formation of LDD spacers 58 (e.g. oxide) along the WL gates 54 in the memory area 24. An N+ implantation is then performed to complete the formation of the drain diffusion regions 60 in substrate adjacent the WL gates 54 in the memory area 24, and source and drain diffusion regions 62/64 in the thin silicon layer 16 to complete the logic devices in the logic area 26. The exposed poly and silicon portions of the structure can be exposed to a metallization process to form a layer of silicide 66 for enhanced conductivity. The final structures are shown in Figs. 15 and 16.

[0020] In the memory area 24, the source and drain regions 46/60 define a channel region 68 there between, with the floating gate 36 disposed over and controlling a first portion of the channel region 68 and the select gate 54 disposed over and controlling a second portion of the channel region 68. The formation of these memory cells is known in the art (see U.S. Patents 6,747310, 7,868,375 and 7,927,994 incorporated herein by reference above) and not further described herein. The memory cells each have a floating gate 36, control gate 40, source region 46, select gate 54, erase gate 52, and drain region 60. In the logic area, each logic device includes a conductive gate 56, source region 62 and drain region 64.

[0021] The above described manufacturing process forms memory cells and logic devices on the same SOI substrate, where the layer of silicon on the embedded insulator layer of the SOI substrate is enlarged in thickness relative to the silicon layer in the logic area. This configuration allows the source and drain regions of the memory cells to extend deeper into the silicon than the source and drain regions in the logic area, to sustain a higher breakdown voltage compared to that for the logic N+ junction. The process also allows for the same polysilicon deposition process to form the erase and select gates in the memory area and the logic gates in the logic area. The raised silicon allows for the formation of a floating gate oxide by using thermal oxidation, CVD, or combination of both because the thermal oxidation will oxidize the silicon and make it thinner. The SL junction will be deeper than logic N+ junction due to thicker silicon and higher HVII implant energy. [0022] It is to be understood that the present invention is not limited to the

embodiment(s) described above and illustrated herein. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may eventually be covered by one or more claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, not all method steps need be performed in the exact order illustrated, but rather in any order that allows the proper formation of the memory cell area and the logic area of the present invention. The memory cells can include additional or fewer gates than described above and illustrated in the figures. For example, the memory cells can exclude the control gate and/or the erase gate. Lastly, single layers of material could be formed as multiple layers of such or similar materials, and vice versa.

[0023] It should be noted that, as used herein, the terms "over" and "on" both inclusively include "directly on" (no intermediate materials, elements or space disposed therebetween) and "indirectly on" (intermediate materials, elements or space disposed therebetween).

Likewise, the term "adjacent" includes "directly adjacent" (no intermediate materials, elements or space disposed therebetween) and "indirectly adjacent" (intermediate materials, elements or space disposed there between). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements therebetween.