METHOD FOR MANUFACTURING ELECTRONIC COMPONENT, PARENT BOARD AND ELECTRONIC COMPONENT

Title:

METHOD FOR MANUFACTURING ELECTRONIC COMPONENT, PARENT BOARD AND ELECTRONIC COMPONENT

Document Type and Number:

WIPO Patent Application WO/2006/011291

Kind Code:

A1

Abstract:

In the manufacturing process of an electronic component where a plurality of conductor patterns are laid in layers through an insulation layer, a conductor pattern layer having a plurality of conductor patterns (4, 5, 7, 8) formed on the layer surface at intervals and insulation layers (10-13) are laid in layers alternately thus producing a multilayer body where a plurality of electronic components (1) are formed collectively of the conductor patterns (4, 5, 7, 8) laid in layers. The multilayer body is pressed with a force acting along the layer direction and then cut according to cut lines set along the boundary of each electronic component (1) thus separating each electronic component (1). In the cutting/removing region (Z) of a parent board for cutting out a plurality of electronic components (1), a removing dummy pattern (18) having a size containable in that region is formed. A floating dummy pattern (15) not connected electrically with the conductor patterns (4, 5, 7, 8) is formed in the electronic component (1) while spaced apart from the cutting/removing region (Z).

Inventors:

KUDO KAZUHIDE (JP)
MATSUNAGA MINORU (JP)

Application Number:

PCT/JP2005/009779

Publication Date:

February 02, 2006

Filing Date:

May 27, 2005

Export Citation:

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Assignee:

MURATA MANUFACTURING CO (JP)
KUDO KAZUHIDE (JP)
MATSUNAGA MINORU (JP)

International Classes:

H01F17/00; H01F41/04; H01G4/12; (IPC1-7): H01F41/04; H01F17/00; H01G4/12

Foreign References:

JP2004186343A	2004-07-02
JPH11243017A	1999-09-07
JPH09289128A	1997-11-04
JPH05198439A	1993-08-06
JPH07122430A	1995-05-12

Other References: