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Title:
METHOD FOR MANUFACTURING INTERCONNECTS
Document Type and Number:
WIPO Patent Application WO/2017/217914
Kind Code:
A1
Abstract:
There is provided a method for manufacturing carbon based via interconnects comprising: providing a first substrate; forming a plurality of catalyst pads on the substrate; growing carbon nanotube (CNT) bundles on the catalyst pads; forming a metal coating on the carbon nanotube bundles comprising a Ti-layer followed by an Au-layer; providing a second substrate; forming via connection through openings in the second substrate, the via connection through openings having the same configuration as the array of catalyst pads; inserting the carbon nanotube bundles into the via connection openings of the second substrate; removing the first substrate such that the carbon nanotube bundles remain in the via connection openings of the second substrate; and infiltrating a metal in the carbon nanotube bundlesby means of copper electroplating

Inventors:
LIU JOHAN (SE)
Application Number:
PCT/SE2017/050608
Publication Date:
December 21, 2017
Filing Date:
June 08, 2017
Export Citation:
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Assignee:
SHT SMART HIGH-TECH AB (SE)
International Classes:
H01L21/768; B81C1/00; C01B32/16; H01L23/498; H01L51/00; B82Y40/00
Other References:
T. WANG ET AL.: "Through-Silicon Vias Filled With Densified and Transferred Carbon Nanotube Forests", IEEE ELECTRON DEVICE LETTERS, vol. 33, no. 3, March 2012 (2012-03-01), pages 420 - 422, XP011422779
Y. CHAI ET AL.: "Carbon Nanotube/Copper Composites for Via Filling and Thermal Management", PROCEEDINGS OF ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, 29 May 2007 (2007-05-29), Reno, USA, pages 1224 - 1229, XP031180651
Y. FENG ET AL.: "Fabrication and electrical performance of through silicon via interconnects filled with a copper/carbon nanotube composite", JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, vol. 33, no. 2, March 2015 (2015-03-01), pages 022004, XP012194530
M. B. JORDAN ET AL.: "Development of seed layer for electrodeposition of copper on carbon nanotube bundles", JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, vol. 33, no. 2, March 2015 (2015-03-01), pages 021202, XP012194275
W. MU ET AL.: "Double-Densified Vertically Aligned Carbon Nanotube Bundles for Application and Integration in 3D High Aspect Ratio TSV Interconnects", PROCEEDINGS OF 2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, 31 May 2016 (2016-05-31), Las Vegas, USA, pages 211 - 216, XP032947548
T. WANG ET AL.: "hrough silicon vias filled with planarized carbon nanotube bundles", NANOTECHNOLOGY, vol. 20, no. 48, November 2009 (2009-11-01), pages 1 - 6, XP020168635
T. WANG ET AL.: "Formation of three-dimensional carbon nanotube structures by controllable vapor densification", MATERIALS LETTERS, vol. 78, July 2012 (2012-07-01), pages 184 - 187, XP028510574
G. ZHONG ET AL.: "Growth of Ultrahigh Density Single-Walled Carbon Nanotube Forests by Improved Catalyst Design", ACS NANO, vol. 6, no. 4, March 2012 (2012-03-01), pages 2893 - 2903, XP055448949
Attorney, Agent or Firm:
KRANSELL & WENNBORG KB (SE)
Download PDF:
Claims:
CLAIMS

1 . A method for manufacturing carbon based via interconnects comprising:

providing a first substrate;

forming a plurality of catalyst pads on the substrate wherein each catalyst pad comprises an array of catalyst areas having a predetermined separation distance;

growing carbon nanotube bundles on the catalyst pads;

forming a metal coating on the carbon nanotube bundles comprising a

Ti-layer followed by an Au-layer;

providing a second substrate;

forming via connection through openings in the second substrate, the via connection through openings having the same configuration as the plurality of catalyst pads;

inserting the carbon nanotube bundles into the via connection openings of the second substrate;

removing the first substrate such that the carbon nanotube bundles remain in the via connection openings of the second substrate; and

infiltrating a metal in the carbon nanotube bundles by means of copper electroplating.

2. The method according to claim 1 , wherein the step of infiltrating a metal in the carbon nanotube bundles is performed before the step of inserting the carbon nanotube bundles into the via connection openings of the second substrate.

3. The method according to any one of the preceding claims, wherein copper electroplating is performed such that a Cu volume ratio of the infiltrated carbon nanotube bundles is in the range of 5 to 90%.

4. The method according to any one of the preceding claims, wherein copper electroplating is performed such that a Cu volume ratio of the infiltrated carbon nanotube bundles is at least 35%. 5. The method according to any one of the preceding claims, wherein the step of electroplating comprises a first plating stage using a first current density and a second plating stage using a second current density, higher than the first current density. 6. The method according to claim 5, wherein the first current density is in the range of 1 - 10mA/cm2.

7. The method according to claim 5 or 6, wherein the second current density is in the range of 30 - 100mA/cm2.

8. The method according to any one of the preceding claims, wherein the predetermined separation distance is at least 1 pm.

9. The method according to any one of the preceding claims, wherein the carbon nanotube bundles are grown by means of CVD.

10. The method according to any one of the preceding claims, wherein the step of removing the first substrate further comprising arranging a tape on the second substrate, covering the end of the openings and adhering to the CNT bundles such that CNT bundles are attached to the tape when the first substrate is removed.

1 1 . A substrate comprising carbon based via interconnects formed by a method according to any one of the preceding claims.

12. A method for manufacturing carbon based via interconnects comprising: providing a substrate;

forming a plurality of via connection openings in said substrate, forming a plurality of catalyst pads in the via connection openings, wherein each catalyst pad comprises an array of catalyst areas having a predetermined separation distance;

growing carbon nanotube bundles on the catalyst pads in the via connection openings;

forming a metal coating on the carbon nanotube bundles comprising a Ti-layer followed by an Au-layer; and

infiltrating a metal in the carbon nanotube bundles by means of copper electroplating to form copper infiltrated carbon nanotube bundles.

13. The method according to claim 12, wherein copper

electroplating is performed such that a Cu volume ratio of the infiltrated carbon nanotube bundles is at least 35%.

14. The method according to any one of claims 12 to 13, wherein the step of electroplating comprises a first plating stage using a first current density and a second plating stage using a second current density, higher than the first current density.

15. The method according to any one of claims 12 to 14, further comprising removing a backside of the substrate, exposing the infiltrated carbon nanotube bundles to form via connections through the substrate.

Description:
METHOD FOR MANUFACTURING INTERCONNECTS

Field of the Invention

The present invention relates to a method for manufacturing metal- carbon based interconnects. Background of the Invention

In microelectronics, the trend is to develop smaller integrated

packages, with a higher density of l/Os. In order to continue this development, three dimensional system integration is now the main concept to achieve this. There are many interconnection technologies such as wire bonding, flip-chip, chip-on-board etc. that can be used to realize such an integration. However, the most promising technology for doing 3D packaging is through-silicon via (TSV) technology, where the TSVs act as paths for signal exchange and power delivery between the stacked chips. TSV technology has been successful in reducing signal delay, enhancing the IC integration and decreasing the overall packaging volume. The further development of TSV technology will accelerate the miniaturization of 3D packages, as well as increasing the number of I/O systems.

The key performance factor for TSV is determined by the filling material. There are various materials that have been used for the TSVs, such as copper (Cu), tungsten (W), and Molybdenum (Mo). Cu is the most common material for filling TSVs due to its excellent electrical conductivity and low process costs. However, the main limiting factor for Cu-through silicon via (TSV) technology is the large difference in the coefficients of thermal expansion (CTE) between Cu and Si, which results in large amounts of mechanical stress in the TSV and the surrounding Si. In addition, electro- migration and skin effects also limit the application of Cu TSVs at high frequencies. Finally, further miniaturization with Cu TSVs is difficult due to the high aspect ratios required.

Since Carbon nanotubes (CNTs) have very low CTE, limited joule heating and are less susceptible to electro-migration, meaning they can withstand high current densities; CNTs address some of the problems associated with Cu TSV technology and are another potential filling material. More importantly, CNTs can be grown at high aspect ratios, meeting the needs for future 3D-IC miniaturization. However, the electrical resistivity of CNT TSVs is several orders of magnitude higher than Cu TSVs due to their highly porous structure. Although vertically-aligned CNTs can be densified, the resistivity of the CNT TSVs is still two orders of magnitude higher than Cu.

Accordingly, there is a need for an improved interconnect material and for a method form manufacturing such interconnects.

Summary

In view of above-mentioned and other drawbacks of the prior art, it is an object of the present invention to provide an improved interconnect, and in particular a method for manufacturing such an interconnect.

According to a first embodiment of the invention, there is provided a method for manufacturing carbon based via interconnects comprising:

providing a first substrate; forming a plurality of catalyst pads on the

substrate; growing carbon nanotube (CNT) bundles on the catalyst pads; forming a metal coating on the carbon nanotube bundles comprising a Ti- layer followed by an Au-layer; providing a second substrate; forming via connection through openings in the second substrate, the via connection through openings having the same configuration as the array of catalyst pads; inserting the carbon nanotube bundles into the via connection openings of the second substrate; removing the first substrate such that the carbon nanotube bundles remain in the via connection openings of the second substrate; and infiltrating a metal in the carbon nanotube bundles by means of copper electroplating.

The present invention is based on the realization that an improved interconnect can be provided where the advantageous effects of carbon nanotubes and of copper are combined by means of the described method. In particular, a carbon nanotube based interconnect which is infiltrated by copper by means of electroplating minimizes mechanical stress in the interconnect as a result of the flexibility of the carbon nanotubes while the electrical conduction properties are similar to those of pure copper.

Furthermore, the thermal expansion of the interconnects is significantly reduced compared to for pure copper interconnects. Moreover, the via interconnects and metal integration can be manufactured at low

temperatures, which facilitates process integration in existing process. The via interconnects may also be referred to as through-silicon vias (TSVs).

That the via connection through openings have the same configuration as the plurality of catalyst pads should in the present context be interpreted to mean that there are openings at locations of the second substrate

corresponding to the location of catalyst pads of the first substrate. Moreover, the openings have substantially the same size and shape as the catalyst pads to enable the metal infiltrated CNT bundles to be inserted into the openings. To further facilitate insertion of the CNT bundles, the via connection openings can be made slightly larger than the catalyst pads.

Furthermore, by performing the metal infiltration process when the CNT are already located in the via openings, the overall conductivity of the via connection may be improved since it is more likely that the metal will fill the entire volume of the via connection opening in comparison to the case where pre-metallized CNT bundles are inserted into the via connection.

According to one embodiment of the invention, the step of infiltrating a metal in the carbon nanotube bundles may be performed before the step of inserting the CNT bundles into the via connection openings of the second substrate.

Thereby, the metallized carbon nanotube bundles can be prefabricated before being inserted into the via openings of the second substrate. Among other things, this has the effect that the copper infiltrated carbon nanotube bundles can be integrated in a substrate without the need for any process steps influencing the substrate. This may for example be

advantageous if the substrate is sensitive to any of the process steps used in the process of growing and metallizing the carbon nanotube bundles. According to one embodiment of the invention a Cu volume ratio may advantageously be in the range of 5 to 90%, and in particular, the Cu volume ratio is preferably at least 35%. As expected, the conductivity of the

interconnects increase with increasing copper ratio. However, the relation between the Cu ratio and thee conductivity is non-linear. In view of this, it has been found that a Cu concentration ratio of 35% is preferred to achieve a conductivity which is sufficient for interconnects. The specific Cu volume ratio can be selected such that the mechanical and electrical properties of the via connection are suitable for the particular application at hand.

According to one embodiment of the invention, the electroplating may comprise a first plating stage using a first current density and a second stage using a second current density, higher than the first current density. By controlling the electroplating to use different plating currents in different plating stages, it can be ensured that Cu ion nucleation occurs slowly in the carbon nanotube bundles in order to form small and uniform Cu grains on the carbon nanotubes.

The first current density may advantageously be in the range of 1 - 10mA/cm 2 , where the electroplating takes place at a temperature of about 25- 30°C to further ensure Slow Cu ion nucleation. The second current density may be in the range of 30 - 10OmA/cm 2 The plating time of the second plating stage is controlled to achieve the desired Cu volume ratio.

According to one embodiment of the invention, each catalyst pad may comprise an array of catalyst areas having a predetermined separation distance. By means of the grid array, the carbon nanotube bundles are separated during growth, which in turn facilitates the electroplating. In particular, the grid array improves the nucleation of the Cu ions such that the surface coverage and thereby the infiltration of the copper into the CNT bundles is improved.

According to one embodiment of the invention, the separation distance between adjacent features of the catalyst pad may be approximately 1 pm which has been found to be sufficient to achieve a high degree of infiltration. According to one embodiment of the invention, the step of removing the first substrate may further comprise arranging a tape on the second substrate, covering the end of the openings and adhering to the CNT bundles such that CNT bundles are attached to the tape when the first substrate is removed. The tape should thus have a higher adhesion to the metallized CNT bundles than the adhesion between the CNT bundles and the catalyst pads. The tape may for example be a thermal release tape configured to release when heated.

According to another embodiment of the invention, there is provided a method for manufacturing carbon based via interconnects comprising:

providing a substrate; forming a plurality of via connection openings in said substrate, forming a plurality of catalyst pads in the via connection openings; growing carbon nanotube bundles on the catalyst pads in the via connection openings; forming a metal coating on the carbon nanotube bundles

comprising a Ti-layer followed by an Au-layer; and infiltrating a metal in the carbon nanotube bundles by means of copper electroplating to form copper infiltrated carbon nanotube bundles.

Hereby, the carbon nanotube bundles are both grown and metallized directly in the via connection openings. With this method, no transfer is needed which is advantageous as the transfer represents a major hurdle for the large scale wafer CNT TSV technology as it requires extremely placement accuracy on a wafer scale. It should be noted that the growth and

metallization process for forming the copper infiltrated CNT bundles is the same for in-via growth as for the case where growth and metallization is performed prior to inserting the CNT bundles into the via connection, and the associated advantages relating to the properties of the via connections are thus the same.

According to one embodiment of the invention, when the CNT bundles are grown directly in via connection openings which does not reach through the substrate, the method may further comprise removing a backside of the substrate, and exposing the infiltrated carbon nanotube bundles to form via connections through the substrate. The backside of the substrate can for example be removed using chemical-mechanical planarization (CMP).

Further features of, and advantages with, the present invention will become apparent when studying the appended claims and the following description. The skilled person realizes that different features of the present invention may be combined to create embodiments other than those described in the following, without departing from the scope of the present invention. Brief Description of the Drawings

These and other aspects of the present invention will now be described in more detail, with reference to the appended drawings showing an example embodiment of the invention, wherein:

Fig. 1 is a flow chart outlining the general steps of a method according to an embodiment of the invention;

Fig. 2 schematically illustrates a manufacturing method according to an embodiment of the invention;

Fig. 3 is a flow chart outlining the general steps of a method according to an embodiment of the invention;

Fig. 4 is a flow chart outlining the general steps of a method according to an embodiment of the invention;

Fig. 5 schematically illustrates a manufacturing method according to an embodiment of the invention; and

Fig. 6 is a graph outlining the resistance and resistivity vs the copper volume ratio for copper infiltrated carbon nanotube bundles manufactured according to embodiments of the invention.

Detailed Description of Example Embodiments

In the present detailed description, various embodiments of and method according to the present invention are mainly described with reference to a method for forming a carbon based via interconnect comprising carbon nanotube bundles infiltrated with copper. Fig. 1 is a flow chart outlining the general method steps of a method according to an embodiment of the invention. The method will be described with further reference to Figs. 2A-H schematically illustrating various steps of the manufacturing method.

The method comprises providing 102 a first substrate 200 illustrated in

Fig. 2A, which for example may be a conventional silicon substrate. A plurality of catalyst pads 204 are formed 104 on the substrate using photolithography. In an example embodiment, an array of circular catalyst pads 204 having a diameter of 200pm was formed. Each catalyst pad 204 has a diameter in the range of 100-500 pm, such as 200 pm and comprises an array of catalyst areas 206, illustrated as the dots in the catalyst pads 204 Fig. 2A. The catalyst areas 206 are separated by gaps of about 2-4 pm to allow Cu to enter in between the grown CNT bundles during the subsequent

electroplating.

The specific process for forming the catalyst pads is as follows: first, photolithography is used to form a circular array pattern, then 10nm AI2O3 and 1 nm Fe are deposited onto the Si substrate 200 through evaporation. After lift-off, a catalyst pattern was obtained on the Si chip.

Next, carbon nanotube bundles 208 are grown 106 using a

commercially available CNT chemical vapor deposition (CVD) system at around 700°C, shown in Fig. 2B. The position, height and quality of the CNTs 208 can be controlled by adjusting the growth temperature and growth time. Here the CNT bundles 208 were grown to several hundred micrometers in height.

Once the CNT bundles 208 are grown, a metal coating 210 is formed

108 on the CNT bundles 206 as illustrated in Fig. 2C. The coating 210 comprises 10nm Ti and 20nm Au sputtered onto the surface of the samples. There are two functions for the coating layer 210, one is that the Ti/Au layer can enhance the wetting ability of the CNTs to the Cu electroplating solution and the other is to act as a conductive layer for the electroplating process. Another important feature is that the overall structure of CNT array remains porous after the sputtering process, which facilitates Cu nucleation between the CNTs.

In the next step, illustrated in Fig. 2E, a second silicon substrate 212 is provided 1 10. Silicon via connections 214, i.e. through-silicon vias (TSVs) were etched through the silicon target wafer 212 using a deep reactive ion etching (DRIE) process. The diameter of via is between 250pm to 300pm to match the diameter of the catalyst pads. It should however be noted that the described method may be used to form via connection having a diameter ranging from a few micrometers up to several hundreds of micrometers.

Before the DRIE process, the target wafer 212 was patterned using standard lithography processes. The via pattern was later used for alignment with previous CNT array patterns for further transfer processes.

Fig. 2F illustrates the CNT bundles 208 inserted 1 14 into the via openings 214 and with a thermal release tape 216 arranged on the top side off the second substrate 212, such that the tape 216 adheres to the CNT bundles 208. Thereby, the first substrate 200 can be removed 1 16 such that the CNT bundles 208 remain in the via connection openings 214 of the second substrate 212 as illustrated in Fig. 2G.

In the final step illustrated in Fig. 2H, a metal is infiltrated 1 18 in the CNT bundles 208 by means of copper electroplating, to form the final copper CNT composite via interconnects 218.

The electroplating process comprises arranging the CNT bundles in copper acetate (2.75mM) electrolyte in acetonitrile under galvanostatic electric field to uniformly seed Cu into the CNT array. The sample was then put into a second aqueous electro-deposition plating setup to grow Cu seeds. The plating temperature is controlled between 25-30°C. For the first step, a very low current density of just 1 -10mA/cm 2 , compared to standard 30- 100mA/cm 2 , was used to ensure that Cu ion nucleation occurred slowly inside the CNT array. For the second step, a current density of 30-100 mA/cm 2 was used to complete the plating process. The speed of plating Cu is in the range of 0.1 pm - 0.6pm /cm 2 to create a uniform Cu grain structure on the CNT bundles. To achieve a copper volume ratio of about 45-50 %, the plating time at the first plating current is in the range of 15 to 20m in and the plating time at the second plating current is in the range of 600 to 650m in.

Fig. 3 is a flow chart illustrating an embodiment of the method where the step of infiltrating 1 18 a metal in the carbon nanotube bundles is performed before the step of inserting 1 14 the carbon nanotube bundles into the via connection openings of the second substrate. Accordingly, both growth and metallization, i.e. Cu infiltration, of the CNT bundles may take place directly on the first substrate as such, before the CNT bundles are arranged in the via openings 214 of the second substrate 212. The

electroplating process can be performed in the same manner as described above with reference to Figs 1 -2.

In alternative embodiment, the CNT growth may take place in the via openings after a first substrate has been arranged together with a second substrate such that the catalyst pads are exposed in the openings of the second substrate. The growth and metallization of the CNT bundles providing the advantageous electrical and mechanical properties is the same for both alternatives.

Fig. 4 is a flow chart outlining the steps of a method according to an embodiment of the invention. The method will be described with further reference to Figs. 5A-D schematically illustrating various steps of the manufacturing method.

The method comprises providing 402 a substrate 502 and forming 404 via connection openings 504 in the substrate 502 as illustrated in Fig. 5A. Here, the openings do not reach through the substrate 502. Instead, catalyst pads 506 are formed 406 at the bottom of the openings 504, illustrated in Fig. 5B.

The CNT bundles 508 are then grown 408 in the openings 504 as illustrated in Fig. 5C. After CNT growth, the CNT bundles are metallized in a similar manner as described above, i.e. by forming 410 a metal coating followed by Cu electroplating to infiltrate 412 and metallize the CNT bundles. It can be assumed that the details of the various process steps are the same as described above in relation to Figs 1 -2.

Fig 5D schematically illustrate the final metalized CNT interconnects 510 after removal of the backside of the substrate 502, for example by means of CMP.

Fig. 6 is a graph illustrating the resistance and resistivity vs the copper volume ratio of Cu-CNT composite interconnects manufactured according to the above described methods. It can be seen that the resistance and resistivity of the Cu infiltrated CNT bundles rapidly approaches the values of pure copper for copper volume ratios above 20%. Accordingly, the metal infiltrated CNT bundles can be tailored to the desired resistivity by controlling the copper volume ratio, such that interconnects having the required electrical performance can be provided. Moreover, the interconnects have a high degree of flexibility also at copper concentration in the range of 50-70%.

Accordingly, the advantageous effects of carbon nanotubes and copper can be combined. It should also be noted that the CNT bundles have a high thermal conductivity, comparable to that of pure copper.

Even though the invention has been described with reference to specific exemplifying embodiments thereof, many different alterations, modifications and the like will become apparent for those skilled in the art. Also, it should be noted that parts of the method may be omitted,

interchanged or arranged in various ways, the method yet being able to perform the functionality of the present invention.

Additionally, variations to the disclosed embodiments can be understood and effected by the skilled person in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.