Title:
METHOD FOR MANUFACTURING LAMINATED ELECTRONIC COMPONENT
Document Type and Number:
WIPO Patent Application WO/2015/033788
Kind Code:
A1
Abstract:
First, a mother sheet (BS1) having a principal surface on which broken lines (BL, BL, …) are defined is prepared. Conductor patterns (CP1, CP1, …) are each formed in a partial region that avoids the broken lines (BL) in the principal surface of the mother sheet (BS1). A ceramic paste (SPS) is applied to other partial regions each crossing over the broken line (BL) in the principal surface of the mother sheet (BS1). Through-holes (HL11, HL11, …) are formed in the mother sheet (BS1) so as to correspond to positions where the ceramic paste (SPS) is applied. A conductive paste is filled into the thus formed through-holes (HL11, HL11, …). This operation is performed on other mother sheets, and a laminated inductor element is produced by laminating the thus produced plurality of mother sheets and cutting the laminated mother sheets along the broken lines (BL, BL, …).
Inventors:
YOKOYAMA TOMOYA (JP)
OHMURA TSUBASA (JP)
OHMURA TSUBASA (JP)
Application Number:
PCT/JP2014/071848
Publication Date:
March 12, 2015
Filing Date:
August 21, 2014
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H01F41/04; H01F17/00; H01F27/29
Foreign References:
| JP2004095960A | 2004-03-25 | |||
| JP2010263000A | 2010-11-18 | |||
| JPH118157A | 1999-01-12 | |||
| JP2002319519A | 2002-10-31 | |||
| JPH08186047A | 1996-07-16 |
Attorney, Agent or Firm:
SAKAI, MASATOSHI (JP)
Boundary Masatoshi (JP)
Boundary Masatoshi (JP)
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