Title:
METHOD FOR MANUFACTURING MEMORY DEVICE USING SEMICONDUCTOR ELEMENT
Document Type and Number:
WIPO Patent Application WO/2022/239198
Kind Code:
A1
Abstract:
The method of the present invention comprises the steps of: forming, on a substrate 20, an Si pillar 26 comprising an N+ layer 21a connected to a source line SL, a P+ layer 22a that is vertically upright and located in the center, and a P layer 25a surrounding the P+ layer 22a; forming, on the P+ layer 22a, an N+ layer 3b connected to a bit line BL and HfO2 layers 28a, 28b that are gate insulation layers and that surround the Si pillar 26; and forming a TiN layer 30a that is a gate conductor layer surrounding the HfO2 layer 28a and connected to a plate line PL, and a TiN layer 30b that is a gate conductor layer surrounding the HfO2 layer 28b and connected to a word line WL. The method of the present invention involves performing: a data-holding operation in which voltages applied to the source line SL, the plate line PL, the word line WL, and the bit line BL are controlled to hold a hole group generated by impact ionization or a gate-induced drain leakage current inside the Si pillar 26; and a data-deleting operation in which the hole group is removed from within the Si pillar 26.
Inventors:
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
SAKUI KOJI (JP)
Application Number:
PCT/JP2021/018249
Publication Date:
November 17, 2022
Filing Date:
May 13, 2021
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
International Classes:
G11C16/04; G11C11/401; H01L21/8242; H01L27/10; H01L27/108
Foreign References:
| JP2008218556A | 2008-09-18 | |||
| JP2006080280A | 2006-03-23 |
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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