METHOD FOR MANUFACTURING MULTILAYER WIRING SUBSTRATE

Title:

METHOD FOR MANUFACTURING MULTILAYER WIRING SUBSTRATE

Document Type and Number:

WIPO Patent Application WO/2015/053084

Kind Code:

A1

Abstract:

　A method for manufacturing a multilayer wiring substrate having: a step (1) for providing an opening for a via hole extending from a metallic foil for an upper layer wiring line to an inner layer wiring line using a conformal method or a direct laser method; and a step (2) for forming a via hole by forming an electrolytic filler plating layer in the opening for a via hole. The formation of the electrolytic filler plating layer in the step (2) is performed by repeating two or more times an operation of lowering the current density for electrolytic filler plating during electrolytic filler plating and then raising the current density, prior to the electrolytic filler plating layer closing the open portion of the opening for the via hole.

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Inventors:

YOSHIDA NOBUYUKI (JP)

Application Number:

PCT/JP2014/075257

Publication Date:

April 16, 2015

Filing Date:

September 24, 2014

Export Citation:

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Assignee:

HITACHI CHEMICAL CO LTD (JP)

International Classes:

H05K3/40; H05K3/00

Foreign References:

JP2009117448A	2009-05-28
JP2013077809A	2013-04-25

Attorney, Agent or Firm:

MINAKAWA Kazuyasu (JP)
Kazuyasu Minagawa (JP)

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