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Title:
METHOD FOR MANUFACTURING SEALING PANEL AND PLASMA DISPLAY PANEL
Document Type and Number:
WIPO Patent Application WO/2007/119676
Kind Code:
A1
Abstract:
This invention provides a sealing panel (100) that can suppress a rise in discharge voltage. The sealing panel (100) comprises a resin material-containing sealing material (20) disposed on the whole periphery in a part between a pair of substrates (1,2). A getter (22), which adsorbs an impurity gas released from the sealing material (20) and an impurity gas passed through the sealing material (20), is formed continuously or intermittently along the inner periphery of the sealing material (20). Further, an ultraviolet shielding wall (24) for preventing ultraviolet light generated within the sealing panel (100) from being incident to the sealing material (20) is formed continuously along the inner periphery of the sealing material (20).

Inventors:
KURAUTI TOSHIHARU (JP)
IIJIMA EIICHI (JP)
Application Number:
PCT/JP2007/057561
Publication Date:
October 25, 2007
Filing Date:
April 04, 2007
Export Citation:
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Assignee:
ULVAC INC (JP)
KURAUTI TOSHIHARU (JP)
IIJIMA EIICHI (JP)
International Classes:
H01J5/20; H01J7/18; H01J9/02; H01J11/02; H01J11/24; H01J11/36; H01J11/46; H01J11/48; H01J11/52
Domestic Patent References:
WO2006019032A12006-02-23
Foreign References:
JP2005228754A2005-08-25
JP2005005259A2005-01-06
JP2005314136A2005-11-10
JP2005302586A2005-10-27
JP2000030619A2000-01-28
JPH11191378A1999-07-13
JP2002358892A2002-12-13
JP2000277020A2000-10-06
JP2003068201A2003-03-07
JP2006107547A2006-04-20
JP2002075197A2002-03-15
Other References:
See also references of EP 2009667A4
Attorney, Agent or Firm:
SHIGA, Masatake et al. (Yaesu Chuo-k, Tokyo 53, JP)
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