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Patent Searching and Data


Title:
METHOD FOR MANUFACTURING SEMICONDUCTOR CHIP
Document Type and Number:
WIPO Patent Application WO/2003/085714
Kind Code:
A1
Abstract:
A semiconductor wafer (W) where circuits are formed in the area divided by streets is split into semiconductor chips having an individual circuit. By interposing an adhesive sheet whose adhesive force is lowered by stimulation between the semiconductor wafer (W) and the support plate (13), the front side of the semiconductor wafer (W) is adhered to the support plate (13), exposing the back side (10) of the semiconductor wafer (W). The back side (10) of the semiconductor wafer (W) with the support plate (13) is ground. After the grinding is finished, the semiconductor wafer is held with the back side (10) up is diced into semiconductor chips. The adhesive sheet is given stimulus to lower the adhesive force and the semiconductor chips (C) are removed from the support plate (13). The semiconductor wafer and semiconductor chips are always supported by the support plate, avoiding damaging or deforming.

Inventors:
FUKUOKA MASATERU (JP)
HATAI MUNEHIRO (JP)
HAYASHI SATOSHI (JP)
OYAMA YASUHIKO (JP)
DANJO SHIGERU (JP)
KITAMURA MASAHIKO (JP)
YAJIMA KOICHI (JP)
Application Number:
PCT/JP2003/004472
Publication Date:
October 16, 2003
Filing Date:
April 09, 2003
Export Citation:
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Assignee:
SEKISUI CHEMICAL CO LTD (JP)
DISCO CORP (JP)
FUKUOKA MASATERU (JP)
HATAI MUNEHIRO (JP)
HAYASHI SATOSHI (JP)
OYAMA YASUHIKO (JP)
DANJO SHIGERU (JP)
KITAMURA MASAHIKO (JP)
YAJIMA KOICHI (JP)
International Classes:
B24B7/22; B24B41/06; H01L21/00; H01L21/301; H01L21/68; H01L21/78; H01L21/304; (IPC1-7): H01L21/301
Foreign References:
JP2000040677A2000-02-08
JP2001200234A2001-07-24
JPH07142623A1995-06-02
Attorney, Agent or Firm:
Sasaki, Isao (KAWAMURA & ASSOCIATES Toranomon Sangyo Bldg. 6F 2-2, Toranomon 1-chome Minato-ku Tokyo, JP)
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