Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2018/220796
Kind Code:
A1
Abstract:
In order to reduce the dimensions of an electrode pattern while suppressing the occurrence of defects and the like, this method of manufacturing a semiconductor device is provided with: a step for applying a resist on an upper surface (10) of a substrate (11); a step for forming an opening (13) in the resist; a shrink agent applying step for applying a heat-shrinkable shrink agent on the resist (12) and filling the opening (13); a shrinking step for heat-shrinking the shrink agent so as to reduce the width of the opening (13); a removing step for removing the shrink agent after the shrinking step; a metal layer forming step for forming a metal layer (18) on the resist (12) and the opening (13) after the removing step; and a step for removing the metal layer (18) on the resist (12), and the resist (12), wherein in the shrinking step, side surfaces of the resist (12) forming the opening (13) are formed such that the side surfaces are curved to protrude toward the center of the opening (13) from central portions in the thickness direction of the resist (12).
Inventors:
UENO TAKAHIRO (JP)
TAMADA NAOHISA (JP)
KITAGAWA MOTOSHI (JP)
TAMADA NAOHISA (JP)
KITAGAWA MOTOSHI (JP)
Application Number:
PCT/JP2017/020480
Publication Date:
December 06, 2018
Filing Date:
June 01, 2017
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H01L21/027; G03F7/26; G03F7/40
Domestic Patent References:
| WO2005045911A1 | 2005-05-19 |
Foreign References:
| JP2008180813A | 2008-08-07 | |||
| JP2013133471A | 2013-07-08 | |||
| JP2000181077A | 2000-06-30 | |||
| JP2009204723A | 2009-09-10 |
Other References:
HAH, JUNG HWAN ET AL.: "Most efficient alternative manner of patterning sub-80nm contact holes and treches with 193nm lithography", JAPANESE JOURNAL OF APPLIED PHYSICS PART 1, vol. 43, no. 6B, 29 June 2004 (2004-06-29), pages 3663 - 3667, XP001232202, DOI: 10.1143/JJAP.43.3663
CHEN, WEI-SU: "Sub-10nm Contact Holes with Aspect Ratio over Sixty Formed by E-beam Resist Shrinkage Techniques", PROC. OF SPIE, VOL. VOL.6519; ADVANCES IN RESIST MATERIALS AND PROCESSING TECHNOLOGY 24, vol. 6519, 15 March 2007 (2007-03-15), pages 651945-1 - 651945-12, XP055634491, DOI: 10.1117/12.708436
CHEN, WEI-SU: "Sub-10nm Contact Holes with Aspect Ratio over Sixty Formed by E-beam Resist Shrinkage Techniques", PROC. OF SPIE, VOL. VOL.6519; ADVANCES IN RESIST MATERIALS AND PROCESSING TECHNOLOGY 24, vol. 6519, 15 March 2007 (2007-03-15), pages 651945-1 - 651945-12, XP055634491, DOI: 10.1117/12.708436
Attorney, Agent or Firm:
TAKADA, Mamoru et al. (JP)
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