Title:
METHOD OF MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/1997/007545
Kind Code:
A1
Abstract:
A method of manufacturing a semiconductor integrated circuit such that the variation of the sheet resistance of polysilicon is small and the reproducibility of the sheet resistance is very high. The method comprises a step of forming a silicon nitride film over the metal interconnection by plasma CVD and a step of heat-treating the wafer at a temperature of 400 �C to 480 �C after the silicon nitride film is formed.
Inventors:
AKAMINE TADAO (JP)
HARADA HIROFUMI (JP)
SATO KEIJI (JP)
INOUE MASAHIRO (JP)
YAMANAKA JUNKO (JP)
SAITO YUTAKA (JP)
HARADA HIROFUMI (JP)
SATO KEIJI (JP)
INOUE MASAHIRO (JP)
YAMANAKA JUNKO (JP)
SAITO YUTAKA (JP)
Application Number:
PCT/JP1996/002264
Publication Date:
February 27, 1997
Filing Date:
August 09, 1996
Export Citation:
Assignee:
SEIKO INSTR R & D CENTER INC (JP)
AKAMINE TADAO (JP)
HARADA HIROFUMI (JP)
SATO KEIJI (JP)
INOUE MASAHIRO (JP)
YAMANAKA JUNKO (JP)
SAITO YUTAKA (JP)
AKAMINE TADAO (JP)
HARADA HIROFUMI (JP)
SATO KEIJI (JP)
INOUE MASAHIRO (JP)
YAMANAKA JUNKO (JP)
SAITO YUTAKA (JP)
International Classes:
H01L27/04; H01L21/318; H01L21/324; H01L21/768; H01L21/822; (IPC1-7): H01L27/04
Foreign References:
| JPS6196756A | 1986-05-15 | |||
| JPS61228661A | 1986-10-11 | |||
| JPS6224661A | 1987-02-02 | |||
| JPS6442851A | 1989-02-15 | |||
| JPH01241860A | 1989-09-26 |
Other References:
See also references of EP 0786811A4
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