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Title:
METHOD FOR MANUFACTURING A SEMICONDUCTOR WAFER
Document Type and Number:
WIPO Patent Application WO/2010/016510
Kind Code:
A1
Abstract:
Disclosed is a semiconductor wafer manufacturing method capable of more suppressing the production of particles caused by a contact mark which is formed in a semiconductor wafer by the contact with the support boat or the like of a heat treatment apparatus.  The semiconductor wafer manufacturing method is characterized by comprising: a chamfering step (S8) of forming a chamfered face at the peripheral edge of the semiconductor wafer; a heat treatment step (S12) of subjecting the semiconductor wafer having passed through the chamfering step (S8), to a heat treatment in an atmosphere of 900 ºC or higher; and a boundary polishing step (S14) of polishing the region which is in the principal face of the semiconductor wafer having passed through the heat treatment step (S12) and is in the vicinity of the boundary between the principal face and the peripheral edge, together with the boundary.

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Inventors:
NAKAYAMA, Takashi (2-1 Shibaura 1-chome, Minato-k, Tokyo 34, 〒1058634, JP)
中山　孝 (〒34 東京都港区芝浦１丁目２番１号　株式会社ＳＵＭＣＯ内 Tokyo, 〒1058634, JP)
SHIOTA, Takaaki (2-1 Shibaura 1-chome, Minato-k, Tokyo 34, 〒1058634, JP)
Application Number:
JP2009/063845
Publication Date:
February 11, 2010
Filing Date:
August 05, 2009
Export Citation:
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Assignee:
SUMCO CORPORATION (2-1 Shibaura 1-chome, Minato-ku Tokyo, 34, 〒1058634, JP)
株式会社ＳＵＭＣＯ (〒34 東京都港区芝浦１丁目２番１号 Tokyo, 〒1058634, JP)
NAKAYAMA, Takashi (2-1 Shibaura 1-chome, Minato-k, Tokyo 34, 〒1058634, JP)
中山　孝 (〒34 東京都港区芝浦１丁目２番１号　株式会社ＳＵＭＣＯ内 Tokyo, 〒1058634, JP)
International Classes:
H01L21/304; B24B37/04
Attorney, Agent or Firm:
SHOBAYASHI, Masayuki et al. (Takase Bldg, 25-8 Higashi-ikebukuro 1-chome, Toshima-k, Tokyo 13, 〒1700013, JP)
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