Title:
METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE
Document Type and Number:
WIPO Patent Application WO/2011/010415
Kind Code:
A1
Abstract:
A method for manufacturing a thin film transistor substrate is provided with: a step of forming a gate electrode (11a) and first wiring on a substrate (10); a step of forming a gate insulating film (12a), which has a contact hole at a position overlapping the first wiring; a step of forming a source electrode (13a) and a drain electrode (13b), which are provided such that the electrodes overlap the gate electrode (11a) and that the electrodes are being spaced apart from each other, and forming second wiring, which is connected to the first wiring via the contact hole in the gate insulating film (12a); a step of forming an interlayer insulating film (15a) by patterning the second insulating film (15) after sequentially forming an oxide semiconductor film (14) and the second insulating film (15); and a step of forming a pixel electrode (14b) by making the oxide semiconductor film (14) exposed from the interlayer insulating film (15a) have a low resistivity.
Inventors:
OKABE TOHRU
NISHIKI HIROHIKO
CHIKAMA YOSHIMASA
HARA TAKESHI
NISHIKI HIROHIKO
CHIKAMA YOSHIMASA
HARA TAKESHI
Application Number:
PCT/JP2010/001878
Publication Date:
January 27, 2011
Filing Date:
March 16, 2010
Export Citation:
Assignee:
SHARP KK (JP)
OKABE TOHRU
NISHIKI HIROHIKO
CHIKAMA YOSHIMASA
HARA TAKESHI
OKABE TOHRU
NISHIKI HIROHIKO
CHIKAMA YOSHIMASA
HARA TAKESHI
International Classes:
G02F1/1368; G09F9/00; G09F9/30; H01L21/336; H01L29/786
Foreign References:
| JP2008176262A | 2008-07-31 | |||
| JP2009099887A | 2009-05-07 | |||
| JP2008040343A | 2008-02-21 | |||
| JP2000164886A | 2000-06-16 | |||
| JP2008040343A | 2008-02-21 |
Other References:
See also references of EP 2458577A4
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
Hiroshi Maeda (JP)
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