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Title:
METHOD FOR MANUFACTURING TRANSISTOR, AND TRANSISTOR
Document Type and Number:
WIPO Patent Application WO/2013/024734
Kind Code:
A1
Abstract:
The purpose of the present invention is to provide a method for manufacturing a transistor in which contact resistance between an organic semiconductor and an electrode is reduced and in which productivity is high. The present invention is a method for manufacturing a transistor comprising the steps of: forming a base film for supporting a catalyst for electroless plating; causing the base film to support the catalyst for electroless plating and performing a first electroless plating; performing a second electroless plating on the surface of the electrode formed by the first electroless plating and forming source and drain electrodes; and forming a semiconductor layer in contact with surfaces of the source and drain electrodes that face each other; the method for manufacturing a transistor being characterized in that: the energy level difference between the work function of the material used in the second electroless plating and the energy level of the molecular orbit used in electron transfer in the material in the semiconductor layer is less than the energy level difference between the work function of the material used in the first electroless plating and the energy level of the aforementioned molecular orbit.

Inventors:
KOIZUMI SHOHEI (JP)
SUGIZAKI TAKASHI (JP)
MIYAMOTO KENJI (JP)
Application Number:
PCT/JP2012/069973
Publication Date:
February 21, 2013
Filing Date:
August 06, 2012
Export Citation:
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Assignee:
NIKON CORP (JP)
KOIZUMI SHOHEI (JP)
SUGIZAKI TAKASHI (JP)
MIYAMOTO KENJI (JP)
International Classes:
H01L21/336; H01L21/28; H01L21/288; H01L29/786; H01L51/05; H01L51/40
Domestic Patent References:
WO2006104068A12006-10-05
WO2010146645A12010-12-23
Foreign References:
JP2009111000A2009-05-21
JP2005150640A2005-06-09
JP2009302169A2009-12-24
Attorney, Agent or Firm:
SHIGA Masatake et al. (JP)
Masatake Shiga (JP)
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Claims: