Title:
METHOD FOR MANUFACTURING TRANSISTOR AND TRANSISTOR
Document Type and Number:
WIPO Patent Application WO/2013/176247
Kind Code:
A1
Abstract:
A method for manufacturing transistors comprises a step for forming a gate electrode, a step for forming a layer including an insulator layer, and a step for forming a source electrode and a drain electrode on the surface of the layer including the insulator layer. At least one of the gate electrode, source electrode or drain electrode is formed by a step for forming a base membrane by coating with a moulding material including a silane coupling agent and a step for electroless plating after a metal which is an electroless plating catalyst has been deposited on the surface of the base membrane. The silane coupling agent comprises a group containing nitrogen atoms and/or sulphur atoms.
Inventors:
KOIZUMI SHOHEI (JP)
SUGIZAKI TAKASHI (JP)
MIYAMOTO KENJI (JP)
KAWAKAMI YUSUKE (JP)
SUGIZAKI TAKASHI (JP)
MIYAMOTO KENJI (JP)
KAWAKAMI YUSUKE (JP)
Application Number:
PCT/JP2013/064466
Publication Date:
November 28, 2013
Filing Date:
May 24, 2013
Export Citation:
Assignee:
NIKON CORP (JP)
International Classes:
H01L21/336; C23C18/16; C23C18/20; C23C18/34; C23C18/44; H01L29/786; H01L51/05; H01L51/40
Foreign References:
| JP2010040897A | 2010-02-18 | |||
| JP2009102720A | 2009-05-14 | |||
| JP2009246123A | 2009-10-22 | |||
| JP2011044524A | 2011-03-03 | |||
| JP2005068494A | 2005-03-17 | |||
| JP2008159683A | 2008-07-10 |
Attorney, Agent or Firm:
SHIGA Masatake et al. (JP)
Shiga Masatake (JP)
Shiga Masatake (JP)
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