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Title:
METHOD FOR MEASURING LINK VOLTAGE
Document Type and Number:
WIPO Patent Application WO/2012/043465
Kind Code:
A1
Abstract:
Link voltages are measured by enhancing the tolerance and responsiveness to switching noises. A period drt⋅T0 is longer than a period dst⋅T0. Two intervals used by a unit voltage vector (V4) in the period drt⋅T0 are used as a first interval and a second interval. A first measurement value (Vmax1) and a second measurement value (Vmax2) of a link voltage (Vdc) in the center of each of the first interval and the second interval are measured. A representative value (Vmax) of the link voltage (Vdc) in a period T0 that includes the period drt⋅T0 is obtained by interpolation from the first measurement value (Vmax1) and the second measurement value (Vmax2). By eliminating this with cos θ, the maximum value for the link voltage (Vdc) is obtained.

Inventors:
SAKAKIBARA KENICHI (JP)
Application Number:
PCT/JP2011/071869
Publication Date:
April 05, 2012
Filing Date:
September 26, 2011
Export Citation:
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Assignee:
DAIKIN IND LTD (JP)
SAKAKIBARA KENICHI (JP)
International Classes:
H02M5/40; H02M7/12; H02M7/5387
Foreign References:
JP2009213252A2009-09-17
JP2010098848A2010-04-30
JP2007312589A2007-11-29
JP2009106110A2009-05-14
JP2008029151A2008-02-07
JP2000014200A2000-01-14
JP2009213252A2009-09-17
JP2010098848A2010-04-30
JP2007312589A2007-11-29
JPH0467021B21992-10-27
JP2009106110A2009-05-14
Other References:
L. WEI; T. A. LIPO: "A Novel Matrix Converter Topology with Simple Commutation", IEEE ISA200 1, vol. 3, 2001, pages 1749 - 1754, XP010561927
See also references of EP 2624431A4
Attorney, Agent or Firm:
YOSHITAKE, Hidetoshi et al. (JP)
Hidetoshi Yoshitake (JP)
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Claims:



 
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