Figure 1 is a block diagram of a prior art phase-locked loop. The reference signals REF1 and REF2 are fed to a selector 11, and the selected signal is fed to a phase comparator 12 for comparing the OUTPUT phases of the selected signal and the output signal of the phase lock. On the basis of the comparison, the phase comparator 12 gives an energized control signal, which is processed with a loop filter 13 before being fed to a voltage-controlled oscillator 14. The oscillator 14 produces a frequency proportional to the control voltage as the output signal OUTPUT. The output signal OUTPUT is further compared with a phase comparator 12 to a reference signal, which is selected with a selector 11. A loop filter 13 is used to limit the effect of momentary interference on the frequency control. In addition, the coupling also comprises a frequency divider 15 between the output signal and the phase comparator 12 for determining the frequency ratio of the reference signal and the output signal.

Phase-locked loops are then given a medium frequency at which the loop functions best and the control voltage of the oscillator is close to zero, and a variation range of the frequency locking, on which the loop is also locked, but the control voltage differs considerably from its midpoint, preferably 0 V.

A known method is to use another, separate phase-locked loop on the path of the reference signal of the actual loop to reduce the phase shift.

A problem with the prior art equipment is the fact that when reference signals are changed, the signals are generally at different phases, and a phase shift occurs at the moment of changing, interfering with the balance of the frequency control of the loop. Another problem is the fact that extra components are needed for reducing the phase shift with the prior art solution.

It is an objective of the invention to provide an advantageous phase-locked loop, due to which the phase shift is reduced as compared to the prior art.

The objective is achieved by a partly analogue and partly digital phase-locked loop intended for several reference signals, in which the phase change of the output signal of the loop is reduced as follows. The output frequency of the loop is fixed with a digital part at the frequency used, a filtered frequency or an average frequency. The reference signals are changed, the signals to be compared are phased by a selection of phase possible due to the higher frequency of the signal to be fed back, the operating point of the loop filter is set and normal operation is resumed.

The invention relates to a method for reducing the phase shift caused by the changing of the reference signal of a digital phase-locked loop. The method of the invention includes the following steps: -loop filtering is interrupted and the output frequency is fixed, -the reference signal is changed, -the moment of initialization for dividing the output signal of the loop, which is fed back and the frequency of which is to be reduced is selected such that the signal with reduced frequency is phased to an opposite phase compared to the reference signal, -loop filtering is initialized to a balance using an offset register, -loop filtering and output frequency control is resumed.

The invention also relates to a digital phase-locked loop with an arrangement for reducing the phase shift caused by the changing of the reference signal, comprising a reference signal selector, a phase indicator, a loop filter, a controlled oscillator and a frequency divider for the feedback signal. According to the invention, it also comprises control logic -for controlling the reference signal selector, -a loop filter for interrupting and resuming the operation, for setting the frequency and adjusting the balance, and

-a controlled gate circuit and a frequency divider, which can be initialized, for reducing the frequency of the feedback signal and for phasing it.

According to the invention, the reference signal is changed almost without a phase shift, because the output signal, which is fed back, is phased to another reference signal at an accuracy whereby the maximum error is the length of the phase divided by the division number of the divider, which is 1215 in this example.

Because the value of the delay register of the loop filter is saved for the duration of the changing of the reference signal, the same value can be used immediately after the signal is changed. When both reference signals behave in the same way, the same value of the delay register is the most suitable estimate for the second reference signal before the calculated value enabled by the processing of many samples of phase differences.

Preferred embodiments of the invention are described in the dependent claims.

In the following, the invention will be described in greater detail with reference to the accompanying drawings, in which Figure 1 is a block diagram showing a prior art phase-locked loop, Figure 2 is a flow chart of a method for reducing the frequency shift caused by the changing of the reference signal of a phase-locked loop, and Figure 3 is a block diagram showing a phase-locked loop according to the invention.

Figure 1 has been discussed above in connection with the prior art.

Figure 2 is a flow chart of a method according to the invention for reducing the phase shift at the moment when the reference signal of a phase-locked loop is changed. In step 21, the operation of the loop filter is interrupted, and the control logic is used to fix the output frequency of the loop by setting the output of the loop filter either at the value of its last active operation or the average value as specified for a certain period of time passed, and the corresponding value is saved in the delay register.

The reference signal is changed in step 22, but the operation of the loop filter is kept as interrupted and the output frequency as constant. The reference signal is led in an otherwise normal manner to the phase detector, whereby the phase of the output signal and the reference signal is shifted in an uncontrolled manner.

In step 23, the phase of the feedback signal, the frequency of which has been reduced, is aligned with the phase of the reference signal by using the possibility provided by the higher frequency of the output signal to start calculation of the divider from a phase which is as accurately as possible at 180° of the reference signal. In a phase-locked loop according to the invention, the objective is to keep the phase difference of the signals being compared as half a phase, or in opposite phases, as accurately as possible. After the phase has been adjusted, a measurement result corresponding exactly to this opposite phase or the desired phase difference occurs in the outputs of the phase detector.

In step 24, the loop filter is initialized so that the offset value is selected to correspond to the measurement value given by the phase detector about the desired opposite phases. The phase difference within the loop filter is minimized.

In step 25, normal operation of the frequency divider and the loop filter is resumed.

Thus the operation of the whole phase-locked loop is resumed at a moment when the signals compared with a phase detector are in the most suitable phases in relation to each other, and the offset value of the loop filter corresponds to a balanced state. Normal operation is thus resumed flexibly.

Figure 3 is a block diagram of a phase-locked loop according to the invention. The figure shows numbered blocks delimited by broken lines, within which there are components marked with letters. In the text, the blocks are referred to by mere numbers, and the components by a combination of a number and a letter. For instance, the signal change switch is referred to as 31A.

The phase-locked loop consists of a reference signal selector 31, a digital phase detector 32, a loop filter 33, a controlled oscillator 34, an initialization gate 35 for the frequency divider, a frequency divider 36 and control logic 37. Here the selector 31 includes a change-over switch 31A and a 1/128-divider 31B. The change-over switch 31A can be controlled by control logic 37. The divider 31B reduces the frequency of the selected reference signal REF1 or REF2 of 2.048 MHz to 16 kHz.

The selected reference signal, the frequency of which has been reduced, is led both to the digital phase detector 32 and from the loop to the divider 36 for the feedback signal via the gate circuit 35. The phase detector 32 comprises, as first in the signal path, a set-reset flip-flop 32A, which is set to the input S with the rising edge of the feedback signal FB, the frequency of which has been reduced, and reset to the input R with the rising edge of the selected reference signal REF, the frequency of which has been reduced. A signal is thus formed at the output Q 1 of the flip-flop 32A, the length of which is proportional to the time difference between the rising edges of the input signals REF, FB, and which allows the operation of the counter 32B at the input EN for its length. The counter 32B is stepped with an output signal OUTPUT, which has a frequency of 19.44 MHz and is coupled to the input CLK, and initialized with the rising edge of the feedback signal FB, which has a reduced frequency and is coupled to the input R. A digital byte is thus produced to the output Q2 of the counter 32B, which is proportional both to the signal of the output Ql and the phase difference of the signals REF, FB at the inputs S and R of the SR flip-flop. The digital byte of the output Q2 is led to the input Dl of the Data flip- flop 32C at the final value of the calculation. The byte is stepped to the output Q3 with a clock signal FB coupled to the input CLK, the output Q3 being the output of the digital phase detector 32.

The output Q3 of the digital phase detector 32 is led to the digital loop filter 33, the offset device 33A therein, the OFFSET of which is set at the time of initialization as the size of the byte of the output Q3. The upper signal path comprises an amplifier 33B, a feedback adder 33C and a delay register 33D. The lower signal path only comprises an amplifier 33E, and both signal paths are added with the adder 33F for producing an output signal. In this solution, the output signal is parallel and 12 bits wide.

The controlled oscillator 34 comprises a D flip-flop 34A, wherein the digital output signal of the loop filter 33 led to the input D2 is stepped with a feedback signal FB to the output Q4. The stepped signal is converted with a D/A converter 34B to the control voltage of the voltage-controlled oscillator (VCO). The oscillator 34C forms a signal OUTPUT, which is fed back in the loop for comparison and the stepping of the counter 32B of the phase detector.

The OUTPUT is fed back with the divider 36, which reduces the 19.44 MHz frequency to the signal FB of 16 kHz by dividing the frequency by 1215. The initialization gate 35 of the frequency divider couples the selected reference signal

REF to the frequency divider 36, as controlled by the enabling signal of the control logic 37 for initializing the divider 36. Initialization with the rising edge of the reference signal REF synchronizes the selected reference signal REF with the feedback signal FB.

The control logic 37 is used to control the activation of both the synchronization gate 35 of the divider 36 and the loop filter 33, and the initialization of the delay register 33D.

Below, the changing of the input signal used for the timing of the output wires of a synchronous digital hierarchy switching device from the signal of the first input wire to the signal of the second input wire is discussed by way of example. A clock signal of, for instance, 2.048 MHz is received from the input wires either directly or by dividing the frequency, and the signal is raised to a frequency of 19.44 MHz in a phase-locked loop. The clock signal of the first input wire, the frequency of which has been reduced, is selected as the first reference signal REF1 and that of the second input wire as the second reference signal REF2. The timing of the output wires is received from the output signal OUTPUT of the phase-locked loop, which follows the reference signals as accurately as possible.

The reference signal REF1 of the first input wire is coupled to the phase-locked loop in order to maintain normal operation, whereby the signal of 2.048 MHz is reduced to a frequency of 16 kHz by the divider 31B to make it function as the reference signal REF selected by the switch 31A. The OUTPUT frequency of the output signal is 19.44 MHz. Changing of the reference signal REF1 of the first input wire to the reference signal REF2 of the second input wire is started by interrupting the operation of the loop filter 33 and by fixing the frequency of the output signal OUTPUT of the loop with the control logic 37. The frequency is fixed by specifying the output of the loop filter 33 in this example at its last value in active operation, approx. 19.44 MHz, and the last suitable value specified for its variation is saved in the delay register Z-1.

The reference signal REF is changed by replacing the first reference signal REF 1 by the second reference signal REF2. This is done by controlling the change-over switch 31A with the control logic 37. The reference signal REF is led in the normal manner to the phase detector 32, and the phase of the feedback signal FB, the frequency of which has been reduced, is aligned with the reference signal REF. This is performed by initializing the starting of the divider 36 with the rising edge of the

reference signal REF, enabled by the gate 35, at the control input EN, by means of the control logic 37, so that the reference signal REF is led for the duration of the initialization to the initialization input R of the divider 36. Due to the frequency of the output signal, 19.44 MHz, which is 1215 times the frequency of the reference signal REF, the alignment of the phase of the feedback signal FB carried out by means of the initialization is accurate, because the initialization is started automatically from the most suitable phase from among 1215 different phases. The coupling of the reference signal REF to the initialization input R is maintained for at least one cycle of initialization and one cycle of calculation of the phase detector.

In order to resume normal operation, it is necessary that at the moment of interruption, a value of the previous operation is saved in the delay register 33D of the loop filter 33, so that the resumed frequency monitoring would immediately function in the most suitable manner.

Normal operation of both the divider 36 and the loop filter 33 is resumed by means of the control logic, and finally the first input wire can be detached.

The degree of inaccuracy in the phase alignment, which is due to the division number of the frequency divider 36, is low at the value 1215 given above, but it can be further decreased by increasing the output frequency and division number of the oscillator 34C.

A phase-locked loop according to the invention is implemented in the system preferably so that the reference frequency selector 31, the digital phase detector 32, the initialization gate 35 for the frequency divider and the frequency divider 36 are located on a programmable logic circuit, but the loop filter 33, the data flip-flop 34A of the voltage-controlled crystal oscillator 34 and the control logic are integrated in a program of a digital signal processor (DSP) using at least 16 bits. In this case, the D/A converter 34B is a circuit provided with a serial input, which receives its input from a signal processor. Because the oscillator 34C must be very accurate, it is preferably a crystal oscillator.

The implementation is not explained here in greater detail, because a person skilled in the art will be able to construct a solution according to the invention on the basis of the above description.

The invention is not limited merely to the above examples of application, but many modifications thereof are possible within the scope of the inventive idea defined by the attached claims.