Owing to current integration technology, it is possible to make an operational image capturing device in integrated form. Such an integrated image capturing device incorporates, on the same chip, a photo-sensor component formed of a set of photo- sensor elements typically organised in the form of a matrix, and a processing component for assuring the operations of capturing images and reading the data captured by the photo-sensor component.

Traditionally, integrated image capturing devices rely on charge transfer techniques. According to these techniques, photo-generated charges are collected and transferred in a determined manner. The most common charge transfer techniques use CCD (charge-coupled device) components or CID (charge injection device) components. Although these devices utilising these components have found numerous commercial applications, they nonetheless have serious drawbacks. In particular, these components rely on non-standard manufacturing techniques, which are, in particular, incompatible with standard CMOS manufacturing processes. Such components are thus obstacles, in terms of costs and manufacturing ease, to the total integration of image sensors.

As a complement to the aforementioned techniques, a concept has been developed around the use of p-n semiconductor junctions as photo-sensor elements, these junctions being commonly called photodiodes. The essential advantage of such elements is their perfect compatibility with standard CMOS manufacturing processes.

Solutions relying on photodiodes as photo-sensor elements are known from the prior art, in particular from the document"A Random Access Photodiode Array for Intelligent Image Capture"by Orly Yadid-Pecht, Ran Ginosar and Yosi Shacham Diamand, IEEE Transactions On Electron Devices, Vol. 38, no. 8, August 1991, pp.

1772-1780, incorporated by reference herein.

This document thus discloses an integrated image sensor in CMOS technology in the form of a single chip. The architecture of the sensor, which is similar to that of RAM memories, is illustrated in Figure 1. This sensor, generally indicated by the reference numeral 1, includes a matrix 10 of pixels arranged in M lines and N columns. This matrix 10 occupies most of the surface of the sensor. A particular pixel

of matrix 10 is read by addressing the corresponding line and column. For this purpose the sensor further includes a line addressing circuit 20 coupled to the lines of matrix 10 and an output bus 30 coupled to the columns of matrix 10, both controlled by a control circuit 40.

Each pixel of matrix 10 has a structure conforming to the illustration of Figure 2a. The pixel, indicated generally by the reference numeral 50 in figure 2a, includes a photo-sensor element PD, a first stage A1, storage means C1 and a second stage A2, The photo-sensor element PD is formed of a reverse biased photodiode which typically operates by collecting the electrons photo-generated during a so-called integration period. First stage A1 is a sample and hold type circuit for sampling, at a determined time, the voltage value present across the terminals of photodiode PD.

This sampled value is stored on storage means C1 which is typically formed of a capacitor. It will be noted that the voltage value stored on capacitor C1 depends on the transfer function of first stage A1 and in particular on the ratio between the value of the capacitance of photodiode PD and the capacitance of storage means C1.

Second stage A2 enables the sampled voltage stored on storage means C1 to be read. The structure schematically described in Figure 2a advantageously allows separation of the detection and reading processes.

The general structure of the pixel illustrated in Figure 2a thus enables an electronic shutter function to be achieved, simultaneously allowing all the pixels of the sensor to be exposed and the signal representing this exposure to be stored in each pixel, for subsequent reading. By means of this structure, one can thus make an image sensor capable of taking snap-shots of a scene, i. e. a sensor perfectly suited to capturing images of objects which are moving with respect to the sensor.

Various embodiments are envisaged and presented in the aforementioned prior art document. Figure 2b shows, in particular, one of these embodiments wherein pixel 50 includes reverse biased photodiode PD and five n-MOS type transistors M1 to M5. Each pixel 50 includes a memory node, designated B, formed of a capacitor (capacitance C1) and protected from the light, for example by a metal protective layer.

According to the aforementioned article, the pixel operates in an integration mode and transistor M1 initialises photodiode PD at a determined voltage before each integration period. Transistor M2 samples the charge accumulated by photodiode PD and stores the signal thereby sampled at the memory node B. Transistor M2 also ensures isolation or uncoupling of photodiode PD and memory node B. Transistor M3 initialises, in particular, memory node B at a determined voltage. Transistor M4 is a source follower transistor and transistor M5 is a line selection transistor and, during the read process, transfers voltage from transistor M4 to an output bus common to all

the pixels in a column. The signals applied to this structure include a high supply voltage VDD and a low supply voltage Vss forming ground, a first initialisation signal TI, a coupling signal SH, a second initialisation signal RST, and a line selection signal RSEL.

A first terminal of photodiode PD is connected to ground Vss and the other terminal is connected to the source terminals of transistors M1 and M2 whose gate terminals are respectively controlled by signals TI and SH. The connection node between photodiode PD and the source terminals of transistors M1 and M2 will be designated by the reference A in the following description. The drain terminals of transistors M1, M3 and M4 are connected to the high supply voltage VDD. The second initialisation signal RST is applied to the gate terminal of transistor M3. The source terminal of transistor M3, the drain terminal of transistor M2 and the gate terminal of transistor M4 are together connected to memory node B of the pixel. The source terminal of transistor M4 is connected, via line selection transistor M5, to the output bus common to all the pixels in a column. The line selection signal RSEL is applied to the gate terminal of transistor M5.

It will be noted that most of the CMOS image sensors adopt a rolling shutter technique, i. e. exposure is effected line after line. Such non-simultaneous exposure inevitably leads to image distortion, in particular when a moving image is captured.

The structure of the pixel illustrated in Figures 2a and 2b is typically operated in accordance with an integration mode, i. e. the photo-sensor elements are all first of all initialised at a determined voltage and then subjected to illumination during a determined period of time, the charges produced by the photo-sensor elements being accumulated or integrated during this period. According to this operating mode, the pixel response can be termed linear. One drawback of this operating mode lies in the fact that the pixel dynamic range is reduced.

One drawback of the structure illustrated in Figure 2b lies in the fact that the pixel sensitivity is relatively reduced and considerably lower less than that of a CCD sensor. Indeed, given that coupling transistor M2 is operated as a switch to fulfil the electronic shutter function, the useful signal produced by the photodiode, i. e. the charge carriers accumulated by photodiode PD, is divided between the capacitors present on pixel nodes A and B on either side of coupling transistor M2, namely capacitor CPD of photodiode PD and capacitance C1 of memory node B.

A first solution enabling the sensitivity of the sensor to be increased consists in increasing the photosensitive surface of the pixel. Another solution, able to be combined with an increase in the photosensitive surface of the pixel, may consist in adding signal amplification electronic circuitry to the pixel. These solutions are

nonetheless unsatisfactory since they go against trends towards miniaturisation and cost reduction. There is thus a need for a solution for increasing the sensitivity of an electronic shutter image sensor of the aforementioned type without thereby increasing the photosensitive surface of the sensor and/or adding amplification electronic circuitry.

An object of the present invention is thus to propose such a solution for increasing the sensitivity of an electronic shutter image sensor of the aforementioned type.

In order to answer this object, the present invention concerns a method for operating a CMOS image sensor the features of which are listed in claim 1.

Advantageous embodiments of the present invention form the subject of the dependent claims.

One advantage of the present invention lies in the fact that the sensitivity of an electronic shutter image sensor using a pixel structure in accordance with the general illustration of Figure 2a is increased without requiring any increase in the photosensitive surface of the sensor, or any additional complication to the electronic circuits.

Indeed, according to the invention, the charge carriers produced by the photo- sensor element are entirely transferred, during the exposure phase, to memory node B provided that the potential of memory node B does not reach the level of the potential barrier defined by the intermediate voltage, designated VINT, applied to the gate terminal of the transistor coupling the photo-sensor element and the storage means. Given that these charge carriers only"see"the capacitance of the pixel memory node, they generate a more significant voltage variation. Via this mechanism, the pixel sensitivity is thus increased.

According to a particularly advantageous implementation of the invention adopting the pixel structure of Figure 2b, transistor M1 placed on the side of the photo-sensor element (in this case photodiode PD) is used jointly with transistor M2 to perform the pixel shutter function. According to this implementation, the charge carriers which continue to be generated by the photo-sensor element are advantageously drained via transistor M1 and consequently do not disrupt the measuring signal stored on the pixel memory node.

Other features and advantages of the present invention will appear more clearly upon reading the following detailed description, made with reference to the annexed drawings, which are given by way of non-limiting example and in which: - Figure 1, which has already been presented, illustrates schematically the conventional architecture of a CMOS image sensor;

- Figures 2a and 2b, which have already been presented, illustrate respectively a basic diagram and a detailed diagram of a known pixel structure of the CMOS image sensor of Figure 1 ; - Figure 2c shows a detailed diagram of a variant of the pixel structure of Figure 2b; - Figure 3 shows a diagram of the evolution of the signals applied to the pixel structure of Figure 2c according to a first implementation of the invention; - Figure 4 shows the potential levels generated by the voltages applied to the transistor gates of the structure of Figure 2c operated in accordance with the implementation mode of Figure 3; - Figures 5 shows a diagram of the evolution of the signals applied to the pixel structure of Figure 2b in accordance with a second, preferred, implementation mode of the invention; and; - Figure 6 shows the potential levels generated by the voltages applied to the transistor gates of the structure of Figure 2b operated in accordance with the second implementation mode of Figure 5.

Figure 3 shows a first implementation mode of the invention for operating an electronic shutter CMOS image sensor with increased sensitivity. This first implementation mode is applied to a pixel structure according to the illustration of Figure 2c. This pixel structure differs from the structure illustrated in Figure 2b in that it does not include the MOS transistor M1 used, in particular, for initialising voltage Vos at the terminals of photodiode PD. It will be understood, nonetheless, that the implementation mode which will now be described in detail can perfectly well be applied to the structure of Figure 2b provided that transistor M1 is maintained in a non-conductive state. It will be seen, however, with reference to Figures 5 and 6, that this transistor M1 can advantageously be used to participate in the electronic shutter function of the image sensor.

It will also be understood that the various implementation modes of the method according to the present invention are not limited to operating a structure like the structure illustrated in Figure 2b or Figure 2c, but can be applied in a similar manner to any type of structure schematically taking the form of the structure illustrated in Figure 2a, i. e. a structure including a photo-sensor element and storage means capable of being coupled to the photo-sensor element at a determined moment in order to produce and store a measuring signal representative of the charge carriers produced by the photo-sensor element during exposure, this structure having at least one MOS transistor connected via its source and drain terminals to photo-sensor element PD, on the one hand, and to storage means C1, on the other hand. The structures

illustrated in Figures 2b and 2c nonetheless constitute a simple and particularly advantageous structure.

Figure 3 thus shows a temporal diagram of the evolution of control signals SH and RST applied respectively to transistors M2 and M3 of the pixel structure of Figure 2c. According to this first implementation mode, control signal SH applied to transistor M2 is maintained, during an initialisation and exposure phase, at an intermediate voltage VINT, the level of which is between the levels of supply voltages Vss and Voo.

Given that this voltage VINT is between the control logic levels, it could be termed, by opposition, the analogue level voltage. Transistor M3 is operated conventionally as a switch, in order to initialise memory node B at a determined initialisation voltage.

More particularly, acquisition of an image occurs firstly by initialising the sensor pixels by applying intermediate voltage VINT to the gate terminal of transistor M2 and by pulsing signal RST applied to the gate terminal of transistor M3 at a high logic level in order to initialise memory node B to a determined initialisation voltage higher than intermediate voltage VINT applied to the gate terminal of transistor M2. This initialisation phase, designated RESET, occurs until instant t2 in Figure 3. Taking account of the voltage applied to the gate terminal of transistor M2, voltage Vos at the terminals of photodiode PD is initialised at a different voltage to the initialisation voltage present on memory node B, in this case a lower voltage than the initialisation voltage.

At instant t1, initialisation signal RST is brought to its low logic level so as to make transistor M3 non-conductive and thus uncouple memory node B from supply voltage Voo. Signal SH is maintained during this so-called exposure phase and the charge carriers produced by photodiode PD begin to accumulate on memory node B.

At instant t2, at the end of a determined period of time, designated AT, the accumulation of charge carriers on memory node B is interrupted by the passage of signal SH to a low logic level, this having the effect of forming a potential barrier between node A where the charge carriers are produced, and memory node B allowing photodiode PD and memory node B to be completely uncoupled.

This storage phase, during which the read operation is performed, is extended until instants t3 and t4 when signal SH again passes to its intermediate level VINT and when initialisation signal RST is again pulsed at the high logic level in order to initialise the pixel.

Figure 4 illustrates schematically the potential levels defined by the voltages applied to the gate terminals of transistors M2 and M3 during the initialisation, exposure and read phases.

Thus, during the initialisation phase (0 < t < t1), nodes A and B are respectively initialised at voltages substantially equal to VINT-VTH and VDD, where VTH is the threshold voltage of transistor M2. During the exposure phase (t1 < t < t2), the charge carriers produced by photodiode PD at node A are entirely transferred to memory node B and accumulate there. During the storage and read phase (t2 < t < t3), the accumulation of charge carriers on memory node B is interrupted by the presence of the potential barrier generated by transistor M2.

According to the invention, the charge carriers produced by photodiode PD are thus entirely transferred, during the exposure phase, to memory node B provided that the potential of memory node B does not reach the level of the potential barrier defined by the voltage applied to the gate terminal of transistor M2. Given that these charge carriers only"see"the capacitance of memory node B, they generate a more significant voltage variation. Via this mechanism, the pixel sensitivity is thus increased.

Figure 5 thus shows a temporal diagram of the evolution of control signals Ti, SH and RST applied respectively to transistors M1, M2 and M3 of the pixel structure of Figure 2b. According to this second implementation mode, control signal SH applied to transistor M2 is continuously maintained at intermediate voltage VINT.

Transistor M3 is operated as previously as a switch in order to initialise memory node B at a determined. initialisation voltage. Transistor M1 is also operated as a switch in order simultaneously to interrupt the accumulation of charge carriers on memory node B and, advantageously, drain the charge carriers so that they do not disrupt the signal present on memory node B. Indeed, without this drainage function, the charge carriers which continue to be produced by the photodiode and accumulate at node A can potentially disrupt the measuring signal stored on memory node B by a diffusion phenomenon in the semiconductor substrate.

The acquisition of an image thus occurs first of all by initialising the sensor pixels by pulsing signal RST applied to the gate terminal of transistor M3 at a high logic level in order to initialise memory node B at a determined initialisation voltage higher than intermediate voltage VINT applied to the gate terminal of transistor M2.

During this initialisation phase RESET, as well as during the subsequent exposure phase, transistor M1 is kept at the non-conductive state, signa) T) being for example kept at a low logic level as illustrated. It will be understood however that one need only apply a voltage to the gate terminal of transistor M1 for it not to be conductive. Assuming that transistors M1 and M2 have the same characteristics, this means that signal TI has to have a level at least lower than intermediate voltage VINT applied to transistor M2. The voltage threshold from which transistor M1 is conductive of course depends on the threshold voitage of the transistor defined by the

dimensional features of the transistor, namely the gate capacitance, the length and width of its channel, as well as the voltage present at its source terminal, i. e. node A, which is dependent, during the initialisation and exposure step, on intermediate voltage VINT applied to the gate terminal of transistor M2 and the dimensional features of transistor M2.

At the end of the initialisation phase, voltage Vos at the terminals of photodiode PD is, in accordance with the above description, initialised at a different voltage from the initialisation voltage present on memory node B, in this case a lower voltage than the initialisation voltage.

At instant t1, initialisation signal RST is brought to its low logic level in order to make transistor M3 non-conductive and thus uncouple memory node B from supply voltage VDD. As previously, the charge carriers produced by photodiode PD then start to accumulate on memory node B.

At instant t2, the accumulation of charge carriers on memory node B is interrupted by the passage of signal TI, to a level such that transistor M1 is made conductive, such as a high logic level. It will be noted again that one need only apply a voltage to the gate terminal of transistor M1 for the latter to be made conductive. In the hypothesis in which transistors M1 and M2 have the same features this then means that the voltage applied to the gate terminal of transistor M1 has to be greater than intermediate voltage VINT. It will also be noted that the voltage applied to the drain terminal of transistor M1 may be different from supply voltage VDD. It will be understood that this voltage must nonetheless be chosen such that the potential generated in the substrate is greater than the potential defined by intermediate voltage VINT applied to the gate terminal of coupling transistor M2.

As already mentioned, the effect of transistor M1 passing to the conductive state is to drain the charge carriers which are continuously produced by photodiode PD via transistor M1 and thus actually to uncouple nodes A and B. Transistor M1 controlled by signal Ti thus, in a way, plays the role of shutter control similar to the function which, until now, was fulfilled solely by transistor M2. More exactly, by controlling the structure in this way, advantage is taken of the intermediate potential barrier generated by intermediate voltage VINT applied to the gate terminal of transistor M2 in order to uncouple nodes A and B.

The storage phase, during which the read operation is performed, is extended until instants t3 and t4 when signal TI again passes to its low logic level, in this example, and when initialisation signal RST is again pulsed at the high logic level in order to initialise the pixel.

Figure 6 illustrates schematically the level of the potentials defined by the voltages applied to the gate terminals of transistors M1, M2 and M3 during the initialisation, exposure and read phases.

Thus, during the initialisation phase (0 < t < t1), nodes A and B are respectively initialised at voltages substantially equal to VINT-VTH and Voo, where VTH is the threshold voltage of transistor M2. As previously, during the exposure phase (t1 < t < t2), the charge carriers produced by photodiode PD at node A are entirely transferred to memory node B and accumulate there. During the storage and read phase (t2 < t < t3), the accumulation of charge carriers on memory node B is interrupted by the passage of transistor M1 to the conductive state and the drainage, via transistor M1, of the charge carriers produced by photodiode PD.

It will be noted that, as soon as signa ! T) again passes to its low logic level at the end of the read phase, the voltage level at pixel node A has to reach its initialisation level again, fixed by intermediate voltage VINT applied to the gate terminal of transistor M2 before a subsequent exposure of the pixel can be undertaken. This "dead time"is directly dependent on the difference between the voltage level applied to transistor M1 during the read phase and intermediate voltage level VINT applied to the gate terminal of transistor M2. The greater this difference, the greater this"dead time". During the read phase, it is thus preferable to apply a higher voltage than, but nonetheless substantially equal to, intermediate voltage VINT to the gate terminal of transistor M1, such that the"dead time"is reduced to a minimum while guaranteeing that the electronic shutter and the drainage of charge carriers occur.

It will be noted however, that the"dead time"of the pixel can be utilised to perform a pre-treatment operation at the level of the pixel. Indeed, the difference between the voltage levels applied to the gate terminals of transistors M1 and M2 could be selected so as to"filter"the signals from the pixels whose illumination level is lower than a determined illumination threshold. Consequently, only the signals emanating from pixels whose illumination level exceeds this illumination threshold will be stored on the memory nodes of the pixels concerned.

For the purpose of this pre-treatment, the steps of the method may, for example, occur as follows, assuming that intermediate voltage VINT is continuously maintained on the gate terminal of transistor M2: - during the initialisation step, memory node B is initialised as before by means of transistor M3 and photodiode PD is initialised by means of transistor M1 ; - during the exposure step, transistors M1 and M3 are both made non- conductive so that the charge carriers accumulate on node A and, if the illumination

level is sufficient and/or the exposure is sufficiently long, are transferred on memory node B; and - during the memory step, transistor M3 is kept in the non-conductive state and transistor M1 is again made conductive so as to interrupt the accumulation (if the illumination level is sufficient) of charge carriers on memory node B and drain the charge carriers which continue to be produced by photodiode PD.

In the various variants which have been presented hereinbefore, the read operation can be performed in accordance with a technique known to those skilled in the art by the name of"Correlated Double Sampling"or CDS. According to this known technique, the read operation of each line is broken down into a first read phase of the voltage present on memory nodes B of the pixels in a line followed by a second read phase during which the memory nodes of the pixels in the line are re-initialised, in theory by means of transistor M3. A signal formed of the difference between the measured sampled voltage and the initialisation voltage of the memory node is then produced for each pixel. This technique blanks the"fixed pattern noise", i. e. the noise present on each pixel of the sensor and which is due to slight differences in sensitivity which may exist between the pixels. Both the line selection signal RSEL and the second initialisation signal RST are thus applied line by line during this read phase.

By way of improvement against the phenomenon of charge carrier diffusion in the semiconductor substrate, it is preferable to use n-well type photodiodes i. e. photodiodes formed in n type wells. This structure offers the advantage of forming a better barrier to the diffusion of charge carriers than a conventionally formed photodiode structure, for example a simple n type diffusion region.

Numerous modifications and/or improvements to the present invention can be envisaged without departing from the scope of the invention defined by the annexed claims. In particular, the pixel structure used by way of example to illustrate the method according to the present invention could be achieved by means of a complementary p-MOS technology or, if required, include additional transistors.