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Title:
METHOD FOR PLATING POLYMER MOLDING MATERIAL, CIRCUIT FORMING COMPONENT AND METHOD FOR PRODUCING CIRCUIT FORMING COMPONENT
Document Type and Number:
WIPO Patent Application WO/2002/070780
Kind Code:
A1
Abstract:
A method for electroless plating the surface of an insulation layer formed by coating a resin coating basic material with a polymer material filled with inorganic filler and diluted with a solvent and then drying the coated basic material, by irradiating the surface of the insulation layer with a laser beam and then depositing the catalyst of electroplating or a method performing electroplating after making conductive a part irradiated with a laser beam. The method comprises a step of forming an insulation layer (24-1) on a resin coating basic material (20), a step of forming a circuit forming part and a via hole (25) in the insulation layer (24-1) by laser machining, and a step of forming a circuit (23-1) by plating the circuit forming part and the via hole (25) thus formed, wherein a circuit forming part (multilayer substrate) is produced by repeating these steps a plurality of times in this order. A multilayer circuit of three or more layers having an arbitrary circuit pattern can be produced easily at a low production cost.

Inventors:
TANAKA HIROKAZU (JP)
HIRONO SATOSHI (JP)
Application Number:
PCT/JP2001/001637
Publication Date:
September 12, 2002
Filing Date:
March 02, 2001
Export Citation:
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Assignee:
OMRON TATEISI ELECTRONICS CO (JP)
TANAKA HIROKAZU (JP)
HIRONO SATOSHI (JP)
International Classes:
C23C18/20; C23C18/16; C25D5/54; C25D5/56; C25D7/00; H05K3/18; H05K3/46; H05K3/00; (IPC1-7): C23C18/20; C25D5/56; H05K3/18
Foreign References:
JP2000212755A2000-08-02
JP2000212756A2000-08-02
JP2000212793A2000-08-02
JPH04183873A1992-06-30
JPS63186877A1988-08-02
US4615907A1986-10-07
JPH08264957A1996-10-11
JPH0936522A1997-02-07
EP0260514A11988-03-23
Other References:
See also references of EP 1371754A4
Attorney, Agent or Firm:
Aoki, Teruo (Miyanishi-cho 2-chome Fuchu-shi, Tokyo, JP)
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