Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
METHOD FOR POLISHING BOTH SIDES OF SEMICONDUCTOR WAFER AND APPARATUS FOR POLISHING BOTH SIDES OF SEMICONDUCTOR WAFER
Document Type and Number:
WIPO Patent Application WO/2017/073265
Kind Code:
A1
Abstract:
A method for polishing both sides of a semiconductor wafer according to the present invention comprises: detecting a load current value of a sun gear or a load current value of an internal gear when both sides of the semiconductor wafer are polished at the same time; calculating a load factor of the sun gear or a load factor of the internal gear from the detected load current value of the sun gear or the detected load current value of the internal gear; and determining, as a polishing endpoint, the time point at which the calculated load factor of the sun gear or the calculated load factor of the internal gear reaches a local minimum value.

Inventors:
SATO MAMI (JP)
Application Number:
PCT/JP2016/079473
Publication Date:
May 04, 2017
Filing Date:
October 04, 2016
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
SUMCO CORP (JP)
International Classes:
H01L21/304; B24B37/013; B24B37/08; B24B49/10; B24B49/16
Domestic Patent References:
WO2014002467A12014-01-03
Foreign References:
JP2004363181A2004-12-24
JP2013188839A2013-09-26
JP2012058932A2012-03-22
JP2009251380A2009-10-29
JPH11248535A1999-09-17
JP2006272227A2006-10-12
JP2012177914A2012-09-13
Other References:
TETSUYA GOSEKI: "PIC de Hajimeru Analog Kairo", 1 August 2014 (2014-08-01), Tokyo, pages 166 - 167 , 283 to 285, ISBN: 978-4-7741-6596-7
TETSUYA OZAWA: "Zukai LabVIEW Data Shuroku Programming", 10 November 2008 (2008-11-10), Tokyo, pages 146 - 147, ISBN: 978-4-627-84821-4
Attorney, Agent or Firm:
SUDA, Masayoshi (JP)
Download PDF:
View/Download PDF      PDF Help



 
Previous Patent: SILICON CARBIDE SEMICONDUCTOR DEVICE

Next Patent: INORGANIC POLARIZING PLATE AND METHOD FOR MANUFACTURING SAME