Title:
METHOD FOR POLISHING SILICON SUBSTRATE AND POLISHING COMPOSITION SET
Document Type and Number:
WIPO Patent Application WO/2017/150157
Kind Code:
A1
Abstract:
Provided are: a silicon substrate polishing method which is capable of reducing PID; and a polishing composition set which is used in this polishing method. A silicon substrate polishing method according to the present invention comprises a preliminary polishing process and a finish polishing process. The preliminary polishing process comprises a plurality of preliminary polishing steps that are performed on a same polishing plate. The plurality of preliminary polishing steps include a final preliminary polishing step that is performed while supplying a final preliminary polishing slurry PF to a silicon substrate. At least one of the total Cu weight and the total Ni weight in the final preliminary polishing slurry PF supplied to the silicon substrate in the final preliminary polishing step is 1 μg or less.
Inventors:
TABATA MAKOTO (JP)
Application Number:
PCT/JP2017/005139
Publication Date:
September 08, 2017
Filing Date:
February 13, 2017
Export Citation:
Assignee:
FUJIMI INC (JP)
International Classes:
H01L21/304; B24B37/00
Foreign References:
| JP2007150153A | 2007-06-14 | |||
| JPH11186201A | 1999-07-09 | |||
| JPH11214338A | 1999-08-06 | |||
| JP2013048291A | 2013-03-07 | |||
| JP2010021487A | 2010-01-28 | |||
| JP2003297775A | 2003-10-17 |
Other References:
See also references of EP 3425658A4
Attorney, Agent or Firm:
ABE Makoto (JP)
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