Title:
METHOD FOR POLISHING SILICON WAFER AND METHOD FOR MANUFACTURING SILICON WAFER
Document Type and Number:
WIPO Patent Application WO/2018/116558
Kind Code:
A1
Abstract:
Provided are a method for polishing a silicon wafer and a method for manufacturing a silicon wafer which are capable of suppressing the occurrence of a step-shaped micro defect. This method for polishing a silicon wafer is characterized by being provided with: a double-sided polishing step for performing a polishing process on the front and rear surfaces of a silicon wafer; a notch part polishing step for polishing a chamfered section of a notch part of the silicon wafer after the double-sided polishing step; an outer peripheral chamfered section polishing step for polishing an outer peripheral chamfered section except for the chamfered section of the notch part after the notch polishing process; and a finish polishing step for finish polishing the front surface of the silicon wafer after the outer peripheral chamfered section polishing step, wherein the notch part polishing step is performed in a state in which the front surface is wet with water.
Inventors:
MORITA TSUYOSHI (JP)
Application Number:
PCT/JP2017/034346
Publication Date:
June 28, 2018
Filing Date:
September 22, 2017
Export Citation:
Assignee:
SUMCO CORP (JP)
International Classes:
H01L21/304; B24B1/00; B24B9/00; B24B37/08
Foreign References:
| JP2014180753A | 2014-09-29 | |||
| JP2010137328A | 2010-06-24 | |||
| JP2005277050A | 2005-10-06 | |||
| JP2010040950A | 2010-02-18 |
Attorney, Agent or Firm:
SUGIMURA Kenji (JP)
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