Title:
METHOD FOR PREDICTING PATH DELAY OF DIGITAL INTEGRATED CIRCUIT AFTER WIRING
Document Type and Number:
WIPO Patent Application WO/2024/011876
Kind Code:
A1
Abstract:
Disclosed in the present invention is a method for predicting a path delay of a digital integrated circuit after wiring. Firstly, physical design and static timing analysis are carried out on a circuit by means of a commercial physical design tool and a static timing analysis tool; timing information and physical information of a path of the circuit before wiring are extracted as input features of a prediction model; a timing and physical correlation of each level of unit in the path is captured by using a Transformer network; a residual prediction structure is used for calibrating a path delay prediction value after wiring; and finally the path delay prediction value after wiring is output. Compared with the traditional static timing analysis process, in the present invention, a path delay after wiring can accurately and efficiently be predicted before wiring, thereby effectively guiding design and optimization of a circuit before wiring, and having important significance for accelerating the design process of the digital integrated circuit.
Inventors:
CAO PENG (CN)
HE GUOQING (CN)
YANG TAI (CN)
HE GUOQING (CN)
YANG TAI (CN)
Application Number:
PCT/CN2023/070101
Publication Date:
January 18, 2024
Filing Date:
January 03, 2023
Export Citation:
Assignee:
UNIV SOUTHEAST (CN)
International Classes:
G06F30/392; G06F30/394; G06F30/396; G06F30/398
Foreign References:
| CN115146579A | 2022-10-04 | |||
| CN114298435A | 2022-04-08 | |||
| CN109710981A | 2019-05-03 | |||
| CN114117943A | 2022-03-01 | |||
| CN114169283A | 2022-03-11 | |||
| CN114218870A | 2022-03-22 | |||
| US20110099531A1 | 2011-04-28 |
Attorney, Agent or Firm:
NANJING RUIHONG PATENT & TRADEMARK AGENCY (ORDINARY PARTNERSHIP) (CN)
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