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Title:
METHOD FOR PREPARING INSULATED GATE BIPOLAR TRANSISTOR OF TRENCH FS STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2014/206177
Kind Code:
A1
Abstract:
A method for preparing an insulated gate bipolar transistor of a Trench FS structure comprises the following steps: forming an FS layer (20) on the back surface of a wafer (10); forming etching slots (12) on the front surface of the wafer (10), and forming a Pbody area precursor (14) between two adjacent etching slots (12); forming through deposition a dense gate oxide layer (30) on the etching slot (12); depositing a polycrystalline silicon gate (40) on the dense gate oxide layer (30); performing injection and spreading on the Pbody area precursor (14), to obtain a Pbody area (50), an area in which the Pbody area (50) directly contacts with the dense gate oxide layer (30) and that is exposed being referred to as a source area precursor (52); performing photoetching, injection, and spreading on the source area precursor (52), to obtain a source area (60); forming a medium block (70) on the front surface of the wafer (10); forming, on the front surface of the wafer (10), a source (16) and a gate (18) that are disposed at intervals; and forming a P+ anode layer (80) and a metal layer (90) on the back surface of the wafer (10). The method for preparing an insulated gate bipolar transistor of a Trench FS structure does not need an epitaxy technique, the productivity is high, and the cost is low.

Inventors:
WANG GENYI (CN)
ZHANG SHUO (CN)
RUI QIANG (CN)
DENG XIAOSHE (CN)
Application Number:
PCT/CN2014/078906
Publication Date:
December 31, 2014
Filing Date:
May 30, 2014
Export Citation:
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Assignee:
CSMC TECHNOLOGIES FAB1 CO LTD (CN)
International Classes:
H01L21/331; H01L21/336; H01L21/8249
Foreign References:
CN102420133A2012-04-18
CN1790737A2006-06-21
CN102024848A2011-04-20
CN102800591A2012-11-28
US20100038675A12010-02-18
Attorney, Agent or Firm:
ADVANCE CHINA IP LAW OFFICE (CN)
广州华进联合专利商标代理有限公司 (CN)
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