METHOD FOR PRODUCING SUBSTRATE-EMBEDDED CAPACITOR, AND CAPACITOR-INTEGRATED SUBSTRATE PROVIDED WITH SAME

WIPO Patent Application WO/2012/014646

A1

The disclosed method for producing a substrate-embedded capacitor includes: a dielectric layer forming step that forms a dielectric layer on a first electrode layer; a second electrode layer forming step that forms a second electrode layer that faces the aforementioned first electrode layer with the aforementioned dielectric layer therebetween; and a thinning step that thins the aforementioned first electrode layer after the aforementioned dielectric layer forming step. The aforementioned thinning step is, for example, an etching step that thins the aforementioned first electrode layer by means of etching. Also, the method may include an annealing step that carries out annealing treatment on the aforementioned dielectric layer after the aforementioned dielectric layer forming step, the aforementioned thinning step being performed after the aforementioned annealing step.

NOGUCHI Hitoshi (C/O SANYO Electric Co. Ltd, 5-5, Keihan-hondori 2-chome, Moriguchi-sh, Osaka 77, 〒5708677, JP)
野口　仁志 (〒77 大阪府守口市京阪本通２丁目５番５号　三洋電機株式会社内 Osaka, 〒5708677, JP)

JP2011/065543

February 02, 2012

July 07, 2011

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SANYO Electric Co., Ltd. (5-5 Keihan-Hondori 2-chome, Moriguchi-shi Osaka, 77, 〒5708677, JP)
三洋電機株式会社 (〒77 大阪府守口市京阪本通２丁目５番５号 Osaka, 〒5708677, JP)
NOGUCHI Hitoshi (C/O SANYO Electric Co. Ltd, 5-5, Keihan-hondori 2-chome, Moriguchi-sh, Osaka 77, 〒5708677, JP)

H01G4/12; H01G4/18; H01G4/33; H05K1/16; H05K3/46

KADOYA Hiroshi (5-5, Keihan-Hondori 2-chome, Moriguchi-sh, Osaka 77, 〒5708677, JP)

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