Description

Method of producing a thin film functional layer

For micro acoustic devices, several piezoelectric materials are commonly used that all have individual strengths and weaknesses with respect to e.g. wave type, Q, pole-zero- distance, spurious modes excited besides the main mode, permittivity, thermal behavior etc. To fulfill demanding specifications it is desirable to use the most suited material for each application, e.g. for bands in a

multiplexer. If different material systems are to be

combined, this is typically only possible by combining separate dies on e.g. a laminate.

High performance surface acoustic wave (SAW) devices with high quality factor and low temperature coefficient

(Temperature Compensated Filters, TCF) can be realized by a thin (0.25ym to 2.10ym) piezoelectric layer (lithium

tantalate, lithium niobate, etc.) on a carrier wafer (e.g. Silicon-, Sapphire-, Quartz-, Ceramics- or glass-wafer) . The carrier wafer should have a low CTE, high thermal

conductivity, low electrical resistivity and high phase velocity .

Between these two layers additional layers, like Si0 ₂ , could be deposited to improve the electrical performance of these components. This layer should have a slow sound velocity; underneath this layer additional layers, like AIN, with high phase velocity could be added and/or layers to reduce the leakage current. By this construction an acoustic energy confinement can be achieved, that results in reduced acoustic losses by

increased quality factor (Q) in combination Temperature Compensated Filters (TCF) compared to standard Surface

Acoustic Wave ( SAW) -filters .

In general the piezoelectric wafer is bonded to the carrier- wafer by plasma activated fusion bonding or similar

processes. Because of the different CTEs (coefficient of thermal expansion) of the two wafer-materials the wafer bonding process is limited close to room temperature.

Otherwise a high wafer bow or even wafer breakage occurs, because the local and global stress exceeds the break- strength of the materials. Especially because of the

anisotropic CTEs of the piezoelectric materials it is not possible to match the CTE in all directions. The global stress, which is induced by the CTE-mismatch, limits the wafer size and the process-window.

After wafer bonding additional annealing processes are required to increase the bond strength in between the different wafer materials.

In currently used methods to solve the problem of CTE- mismatch the two wafers are bonded together close to room temperature. After annealing and grinding/polishing in several steps the wafer is finished. Thus several steps are required .

For such a process, wafer size and minimizing the annealing- /grinding-/polishing-steps are still limited by the global warpage and thus by the stress. The grinding process is limited by the bond-strength, which is also related to the annealing temperature.

Lastly the complete stack with the two wafers has to be singulated to yield single chips.

It is an object of the present invention to provide a method of fabrication a thin film functional layer. Another object is to provide a wafer bonding process that is more simple and not limited in view of wafer size and CTE-mismatch as much as the currently used wafer bonding processes.

At least one of these objects is solved by a method according to claim 1. Advanced features and advantageous embodiments of the invention are given in further claims.

The general idea of the invention is to reduce the stress that builds when two large area surfaces with different CTEs are wafer bonded together by wafer bonding. This can be done by structuring one of the two surfaces to be bonded together by structuring lines to partition this surface into a regular array of sections and/or to bond the already thinned layer to the carrier wafer by using an additional temporary wafer. As a consequence, the stress which is nearly proportional to the square of the maximum distance between two edge points of a bonded surface segment is substantially reduced when compared with two continuous wafer surfaces.

The first wafer comprises a piezoelectric functional layer on a carrier or a piezoelectric wafer.

The given method of bonding two wafers together comprises the steps of: a) providing a first wafer comprising a functional layer b) providing a second wafer comprising a carrier material having a bonding surface, wherein one surface of the first or second wafer is partitioned by structuring lines into a regular array of sections

c) bonding the first wafer to the bonding surface of the second wafer such that the partitioned surface

constitutes one of the bonded surfaces

d) reducing the thickness of the functional layer of the first wafer until a thin film functional layer of a desired thickness is achieved.

An alternative method of bonding two wafers together comprises the steps of: a) providing a first wafer comprising a functional layer b) providing a second wafer comprising a carrier material having a bonding surface, wherein the surface of the first wafer is partitioned by structuring lines into a regular array of sections

c) bonding the first wafer to the bonding surface of the second wafer such that the partitioned surface

constitutes one of the bonded surfaces

d) reducing the thickness of the functional layer of the first wafer until a thin film functional layer of a desired thickness is achieved.

The total stress produced by the wafer bonding process that can build up between two edges of a bonded surface area is substantially reduced as the distance between two bonded edges complies with the distance between a first structuring line and an adjacent second structuring line. When compared to the stress that can build up over the whole diameter of a wafer a strong stress reduction is achieved. Therefore, the warpage of the wafer is also reduced.

The functional layer of the first wafer comprises a material that supports the function of an electric device made

therefrom. Hence, this material is essential for the

operation and such an electric device can be manufactured from the resulting thin film functional layer.

The structuring lines are provided by the surface of the first wafer. The sections defined thereby can correspond to the size of a single device or multiples of the device singulated from the wafer after finishing the wafer scale manufacturing steps. The depth of the structuring lines is deep enough to allow a stress release at the structuring lines. These lines correspond to the dicing lines along which the final arrangement is separated in single chips. Hence, the structuring lines strongly anticipate the singulation step and hence, the singulation is facilitated.

In step d) the thickness of the functional layer is reduced to a desired final thickness which is necessary for the electric device to be manufactured from this functional layer or on this functional layer. At the latest after step d) the structuring lines are exposed from the back as the depth of the structuring lines corresponds at least the final

thickness of the thin film functional layer.

According to an embodiment step a) and/or b) comprises providing an additional layer deposited onto the first wafer and/or onto the bonding surface of the second wafer. Such an additional layer on the functional layer may enhance or facilitate the bonding. Moreover the additional layer may provide a function or an advantage to the final electric device manufactured from the functional layer.

The additional layer may comprise one or more layers that are chosen from Si02, SiN, AIN, Glass, Ceramic, Polysilicon and/or Silicon, e.g. doped Silicon.

A preferred method of reducing the thickness of the first wafer in step d) is grinding, lapping and/or polishing.

The advantage is that grinding allows to easily control the achieved thickness reduction. Further, grinding results in a plane surface. The roughness of the grinded surface can be further reduced by polishing and/or lapping after grinding.

According to an embodiment step a) comprises the following sub-steps :

al) providing a functional wafer having a functional layer

a2) grooving the structuring lines (SL) into the

functional layer to partition the surface into the regular array of sections (SC)

a3) providing a high precision intermediate carrier wafer

a4) temporarily bonding the functional wafer with the optionally partitioned front side surface to the

intermediate carrier wafer

a5) after bonding reducing the thickness of the

functional wafer from the back; thereby optionally exposing the structuring lines and yielding the first wafer comprising a thin film functional layer of a desired thickness,

and wherein step d) comprises

dl) de-bonding of the intermediate carrier wafer to optionally expose again the structuring lines.

Here, steps a2 is optional and can be omitted as the

structuring lines can be produced in the first wafer that results as an intermediate product after step a5. However, when performing step a2) the stress can be further reduced.

In this embodiment after step a5) an arrangement is achieved that is similar to the arrangement that results after step d) of the general method. On the intermediate carrier wafer a regular array of thin film sections of the functional layer is achieved. Each section may be totally separated from the neighboring section by the structuring lines.

The use of such an arrangement in a further wafer bonding process wherein the functional layer is bonded to the surface of the final carrier wafer results in further advantages. A surface of the functional layer after step a5) can be made very even and the thickness of the functional layer is very homogenous over the entire first wafer. By bonding this surface to the final carrier that is a high precision wafer with an according evenness, the bonding step is facilitated and the bonding strength is increased. Further, as the sections of the functional layer are totally separated, the stress within a section of the functional layer after

carrying out the bonding process is further reduced. This advantage can be used to perform the annealing process directly after wafer-bonding at a higher temperature to improve the bonding strength without extending over the maximum stress limit that is acceptable for the total carrier wafer and the whole arrangement of structured functional layer on intermediate and final carrier wafer as well.

After de-bonding of the intermediate carrier wafer in step dl), the intermediate carrier wafer, which may also be a high precision wafer, can be used again in a further process or a further wafer bonding process according to step a4) .

The intermediate carrier wafer may comprise the same material as the final carrier. In this case, step a5) comprises bonding two identical materials having no thermal mismatch such, that the thermal stress can build up only by the thin functional layer in-between. It only needs to use a temporary bonding process that allows an easy de-bonding after step dl) . Such an intermediate bonding may use an adhesive or another volatile agent. Such an adhesive or volatile agent can be chosen such that according to step c) the adhesive or volatile agent is removed by evaporation, decompensation by LASER or by transforming the adhesive into gaseous or liquid products .

According to a further embodiment the method comprises the following steps:

a21) providing one or more first functional wafers a22) forming the structuring lines through the total wafer thickness of at least one first functional wafer such that single or multiples of the chips with a functional layer are yielded

wherein step c) comprises

c2) bonding the single or multiples of the chips to the bonding surface according to a regular array by chip-to- wafer-bonding to form a first wafer-like arrangement wherein step d) comprises

d21) reducing the thickness of the array of single or multiples of the chips by grinding, lapping and/or polishing .

In this embodiment the first wafer like arrangement is not a through-going functional wafer, but a wafer-like arrangement of single chips each comprising a functional layer or a functional material. The different first functional wafers may differ in their functional material or may be of the same material but have a different crystallographic orientation. Hence, the resulting first wafer like arrangement may

comprise sections of different materials or of different crystallographic orientation. When two such different

sections are combined on a single chip after singulation of the thinned first wafer some advantageous new material combinations are possible.

Different piezoelectric materials, e.g. LiTaCb and LiNbCb or different cut angles that have different properties may be combined on a single carrier wafer for further processing of e.g. thin film SAW (TFSAW) devices. The different properties can be utilized in individual resonators or filters combining the advantages of two different piezoelectric materials. Each of the two different materials may be selected to e.g. have spurious modes only in frequency regions that are not

critical with respect to specification limits. Further, it is possible to use different materials for producing devices that use different wave types for different functions. These different functions may be combined within a filter, a duplexer, a multiplexer, an extractor, or a notch context.

For example, different wave types or modes may be used within one device like Rayleigh-, Lamb-, Love-, shear or longitudinal/ volume (BAW) modes. The combination of the different materials and their different advantages on the same carrier wafer allows for higher integration density (less space consumption) and less parasitic electromagnetic effects from interconnections through e.g. a laminate.

Coming back the stress issue: Compared with a wafer bonding process over the entire surface of the two wafers, this embodiment has the advantage that each of the single chips can be bonded separately and a bonding stress only depends on the dimensions of a single chip and not on the dimension of the whole wafer. Stress impacting onto one single chip has no additional impact onto a neighboring single chip and hence the stress after bonding due to thermal mismatch is

restricted to the stress that can build up over the dimension of one single chip only.

A further advantage refers to the possibility of singulating single chips from different first wafers and combining the single chips of two or more first wafers in a wafer-like arrangement with a total area that is greater than the area of a single first wafer comprising a continuous functional layer. In other words, the further proceeding with the first wafer or wafer like arrangement can be carried out with a higher wafer size than is possible with a wafer having a continuous functional layer whose diameter or size is restricted by the crystal growing process of a piezoelectric wafer of by the process of forming a carrier with a

continuous functional layer.

Some materials are only available with small wafer sizes, which is a disadvantage in view of the throughput and hence in view of efficiency and costs. Another advantage is that higher annealing temperatures can be used after the bonding of single chips to the carrier wafers because of the lower size of the single chips compared to the area of a whole (first) wafer.

In the following steps the wafer-like arrangement of single chips bonded to the carrier wafer can be handled like a continuous wafer. Hence, the wafer-like arrangement can be processed in a unitary way like a single wafer. Hence, step dl) is performed over the whole area of the wafer-like arrangement .

In a further advanced embodiment similar to the above- described embodiment, one or more first functional wafers are provided. These wafers are singulated into single chips or pieces comprising multiples of the chips by cutting the structuring lines through the total wafer thickness of the at least one functional wafer. Thereby single chips or multiples of the chips with a functional layer are yielded. These single chips are then temporarily bonded to the surface of an intermediate carrier wafer in a regular array to form a first wafer-like arrangement. After this step the thickness of this array can be reduced by grinding, lapping and/or polishing the single chips from the backside. Thereafter, this wafer like arrangement of temporarily bonded single chips is transferred to a final carrier wafer by bonding the first arrangement with the surface of the array of single chips to the bonding surface of the final carrier wafer. In a

following step the temporary bond has to be released and the intermediate carrier wafer de-bonded.

In an alternative method the reduction of thickness of the wafer-like arrangement of single chips can be carried out after the final bonding to the final carrier wafer and after de-bonding of the intermediate carrier wafer.

The first wafer or the functional layer of the first wafer comprises at least one piezoelectric material. The second wafer, which is a carrier wafer, comprises a carrier material which is chosen from the group of Si-, PolySi-, Glass-, Ceramic-, Sapphire-, Quartz-, LiTa0 ₃ - or LiNb0 ₃ -wafers .

Further, the second wafer has a high precision surface and low total thickness variation which is a plane without distortion and has a very low roughness. Such a second wafer can be produced in a high precision process or can be

selected from a larger production lot by withdrawing those wafers that do not meet the specification.

A functional layer comprising a piezoelectric material can be used for the production of devices working with acoustic waves. Such thin film acoustic wave devices only need a small thickness of the functional layer that is about 0.2 to 0.6 of the wavelength.

A preferred final thickness of the functional layer in the ready-manufactured device is between 0.25ym to 2.10ym.

After the last step that is after the final bonding step and reduction of thickness the total arrangement can be annealed to enhance the bonding strength.

In a preferred embodiment the structuring lines are cut-in by dicing. To avoid damage of the surface of the functional layer during the dicing step, a temporary protection layer can be applied to the first wafer before cutting-in the structuring lines. After this dicing step the temporary protection layer can be removed and an undamaged surface of the functional layer results. This is important because this surface is the surface that is bonded to the bonding surface of the carrier wafer. Hence, no intermediate step is

necessary after removal of the protection layer which can be done by dissolving the protection layer in a solvent.

It is to be noted that the method of wafer bonding can be performed without the need of sawing or grooving.

In the following the invention is explained in more detail with reference to the embodiments and the accompanying figures .

The figures are schematic only and not drawn to scale. Single elements may be depicted as enlarged or reduced in size.

Figure 1 shows cross-sectional views through the wafer arrangement at different method steps according to a first variant ,

Figure 2 shows different steps of a second variant,

Figure 3 shows different steps according to a third variant,

Figure 4 shows different method steps according to a fourth variant , and

Figure 5 shows different method steps according to a fifth variant ,

Figure 6 shows different method steps according to a sixth variant . Figure 7A shows a partitioned thin-film functional layer on a standard carrier wafer,

Figure 7B shows a partitioned thin-film functional layer on a high precision carrier wafer,

Figures 8A to 8D illustrate the possibility of wafer handling without the need for grooves,

Figure 9 shows two functional wafers and a first wafer with chip sections originating from the two functional wafers,

Figures 10A to 10C show different patterns of how different first and second chip sections or different pieces comprising a multitude of first or second chip sections may be arranged on a common carrier wafer,

Figure 11 shows a carrier chip section comprising a first and a second chip section originating and singulated from two different functional wafers,

Figure 12 shows a carrier chip section comprising a first chip section and a semiconductor device formed in a surface section of the carrier wafer adjacent to the first chip section .

Figure 1 shows, in a cross-sectional view, different process steps of a first variant of the new method. Figure 1A shows a first wafer W1 that comprises a functional layer. It is preferred that the first wafer consists at least mainly of the material of the functional layer but may be provided with further layers to the interface of the second wafer. The functional layer is a layer which is assigned to represent a functional substrate material for an electric device. In the first embodiment the functional wafer is a piezoelectric wafer made of lithium tantalate, lithium niobate or other piezoelectric materials. The first wafer W1 has a first thickness dl which is sufficient to allow a secure handling thereof but can be as low as possible. But the operation of the method does not depend on the real thickness dl of the first wafer W1.

Figure IB shows the first wafer W1 after grooving lines SL in one surface thereof. The structuring lines partition the surface of the first wafer W1 into a regular array of sections SC. As the structuring lines SL are only for separating the sections from each other, they are of a minimal width depending on the tool which is used to produce the structuring lines SL. A typical width of such a

structuring line that is produced by dicing is about 100 ym or less. The structuring lines SL are made down to a depth that is at least the thickness d2 of the later functional layer, as it is useful and desired for making an electrical device therefrom. In the example of the piezoelectric material the desired electric device is a SAW device (SAW = surface acoustic wave), for which a thickness of about 0.25 ym to 2.1 ym is sufficient. Preferably the structuring lines SL are formed with a depth that is as deep as possible without reducing the mechanical stability of the first wafer W1 under an acceptable limit. All sections SC have the same or multiples of the dimension and the same or multiples of the area which is the area necessary for forming an electric device on a functional layer of said area. In figure 1C a second wafer W2 is provided comprising a carrier material and may be provided with further layers to the interface of the first wafer. The carrier material is rigid and useful for forming a substrate of the later electric device. Optionally, the second wafer W2 has a plane surface with low roughness. A preferred material for the second wafer is chosen from Si-, PolySi-, Glass-, Ceramic-, Sapphire-, Quartz-, LiTa03- or LiNb03-wafers .

The first wafer Wl, as shown in Figure IB, is now bonded to the bonding surface BS of the second wafer W2 such that the surface with the structuring lines SL faces the second wafer W2 in the resulting wafer stack. The wafer bonding is preferably done at low temperatures to avoid too much stress produced by a mismatch of the different CTEs. A perfect match of first and second wafer is normally impossible because of the isotropic properties of the piezoelectric material which has different coefficients of expansion along different crystal axes thereof. The carrier material itself is usually isotropic .

In the next step, the first thickness D1 of the first wafer Wl is reduced from the back until a functional layer of a desired second thickness d2 is achieved. Reduction of thickness can easily be done by grinding, lapping and/or polishing the first wafer Wl from the backside. Figure IE shows the arrangement after thinning. As the depth of the structuring lines has been greater than the thickness d2 of the remaining functional layer, the structuring lines SL are exposed by the grinding process. A polishing and/or lapping step of the top surface may follow to produce a plane surface with low roughness which is useful for the acoustic devices.

A regular array of thin film sections SC is yielded. Figure 2 shows a second variant of the method which is similar to the first variant. Figure 2A shows a first wafer W1 comprising a functional layer or consisting of a

functional material having a thickness of dl .

Figure 2B shows a carrier wafer W2. On the bonding surface BS thereof, a regular grid of structuring lines SL is produced similar to the structuring lines SL in Figure IB in the first wafer W1. Here too the bonding surface BS is partitioned into sections that have preferably the same dimensions according to the dimensions of a desired later electric device.

In the next step, the first wafer W1 is bonded to the bonding surface BS of the second wafer W2 by using a proper bonding technology. It may be useful to provide one of the two surfaces to be bonded together with an intermediate layer that can enhance the bonding process or enhance the bonding strength. Such an intermediate layer may be a very thin layer of about a few nanometers and need not have a further

function. But also there may be further layers at the

interfaces of wafers

Figure 2C shows the two wafers W1 and W2 after bonding to a wafer stack; there may be further layers in the interface of the two wafers to improve the electro-acoustical performance of the device.

In a next step, the thickness dl of the first wafer W1 is reduced to a thickness d2 according to the desired thickness of the later electro-acoustic device to be manufactured from the functional layer. The first variant of the method results in a thin film functional layer which is already structured in sections of the desired dimension for the electro-acoustic device in variant 1 (Figure IE) . According to the second variant, and shown in Figure 2D, the functional layer is continuous over the whole wafer size. However the second wafer W2 is

partitioned by the structuring lines into segment of the desired dimension of the later singulated electric device to be manufactured from the functional layer on the second wafer that is a carrier wafer. Here too, stress can only build up over the dimension of a section. In both variants the surface of the functional layer is ready for the fabrication of the electro-acoustic device thereon, e.g. by depositing metal structures for electrodes, resonators and other elements.

In a third variant, the piezoelectric substrate of the first functional wafer W1 is optionally half-cut-diced like in the first embodiment according to figure lb and temporarily bonded at room temperature to an intermediate wafer IW having optionally the same CTE as the later second wafer W2. Then the functional layer of the first wafer is reduced in

thickness by grinding, lapping and/or polishing to expose the optionally structuring lines SL from the back. This stage is depicted in Figure 3F which is similar to figure IE of the first embodiment. However, the partitioned thin functional layer is bonded to the intermediate wafer IW instead of the second wafer W2.

It is to be noted that a variant without the need of grooving or sawing is possible, e.g. as shown in Figure 8A, 8B, 8C, and 8D: Figure 8A illustrates the possibility of the

temporary bonding of the piezoelectric top wafer to an additional carrier wafer at room temperature to avoid thermo- mechanical stress; a high precision wafer (low total

thickness variation, TTV) is used to reduce the thickness variation in the subsequent grinding/polishing sequence; the additional carrier wafer has the same or similar CTE as the final carrier wafer. Figure 8B illustrates the possibility of the grinding and/or polishing of the piezoelectric top wafer. Figure 8C illustrates the possibility of the bonding of temporary bonded sandwich-wafer to the final carrier wafer; elevated temperatures could be used; the global stress is avoided because both carrier wafers have the same/similar CTE; the TTV of the final carrier wafer is not critical anymore. Figure 8D illustrates the possibility of the de bonding of the first carrier wafer; this high precision and expensive wafer could be reused for the next wafers.

In the next step a second wafer W2 is provided forming the final carrier wafer as shown in figure 3H. According to figure 3G, the intermediate wafer IW with the optionally grooved thin film functional layer is bonded to the second wafer W2 of a final carrier material. This bonding step can be carried at elevated temperatures without producing a global stress over the wafer surfaces because the functional layer is sandwiched between two wafers having optionally the same or similar CTE.

In the next step as shown in figure 31 the intermediate wafer IW is removed from the partitioned or structured functional thin film layer by de-bonding.

Figure 31 shows the resulting structure of a partitioned thin film functional layer SLA on the second wafer W2 which is the final carrier wafer. Final wafer means that after singulating single chips from this arrangement the carrier is diced into sections that remain part of each singulated chip. The temporary bonded intermediate wafer IW can be removed without damage from the partitioned thin film functional layer SLA and thus can be reused as intermediate carrier again in a further cycle. Hence, the intermediate wafer IW can be a high precision wafer with a very small thickness variation. Reusing this intermediate wafer saves a lot of costs as the additional high precision intermediate wafer IW causes costs only one time and can then be reused for a lot of times.

Figure 4 shows a fourth variant of the method. According to figure 4A a functional wafer FW having a functional layer or a consisting of a functional material is provided.

Structuring lines SL are diced throughout the whole thickness of the functional wafer FW to produce single sections or single chips CH of the functional wafer that are totally separated from each other. Figure 4B shows a number of such single chips CH.

In the next step the single chips CH are transferred onto the top surface of a second wafer W2 comprising a carrier

material. There, the single chips CH are arranged to form a regular array of single chips CH. The second wafer W2 need not comply with the original dimension of the functional wafer FW and can thus have a greater diameter. Hence, a larger surface area of the second wafer W2 allows to arrange a higher number of single or multiples of the chips CH than the number of single chips CH that can be singulated from a single functional wafer FW alone.

Figure 4C shows a cross-section through a second wafer W2 with the single chips CH arranged thereon. Here, the single chips form a wafer like arrangement WLA. Then the final bonding process can be done by heating the second wafer up to an elevated bonding temperature. The temperature can be set high enough to achieve the desired bonding strength as the single chips CH can only produce local stress and no stress is expected to build up over the entire second wafer W2.

Alternatively, each single chips CH or groups of single chips CH can be bonded to the second wafer W2 in a chip-to-wafer bonding process. But temporary bonding the single chips CH in a desired arrangement before finally bonding them to the second wafer W2 is preferred. For performing a temporary bonding a volatile agent or a volatile adhesive can be used.

In the next step the second wafer W2 with the wafer like arrangement WLA of single chips CH bonded onto its surface is subjected to a thickness reduction of the functional layer. Like in the first three variants described above, the

thickness reduction can be done by grinding from the top for example. A polishing/lapping step may follow. Figure 4D shows the carrier wafer (second wafer W2) with the regular array of thin film sections of the functional layer. This variant has the advantage that no stress extending over the whole wafer can arise during the bonding step such that better bonding conditions and higher temperatures can be used. Thereby a higher bonding strength can be achieved.

Similar to the third variant, the arrangement as shown in Figure 4D can be submitted to a further wafer bond process wherein a final carrier wafer (second wafer W2) is provided (figure 5E) and bonded to the top surface of the partitioned thin film functional layer SLA as shown in figure 5F. Figure 5G shows the thin film functional layer SLA structured in a regular array of sections and sandwiched between an intermediate carrier wafer ICW and the final carrier wafer CW.

In the next step the intermediate carrier wafer ICW is removed by de-bonding from the final carrier wafer CW. This variant can be made easier when using a temporary bonding step for the single chips onto the second wafer W2. Figure 5h shows the achieved arrangement.

Figure 6 shows a slightly different variant of the process of Figure 5 and the fifth variant. Here a final carrier wafer CW is provided as shown in Figure 6D and wafer bonded to an arrangement as shown in Figure 6E which is according to figure 4C where single chips CH of a thickness dl and

arranged in a wafer like arrangement WLA are bonded to a second wafer W2. Figure 6F shows the two wafers bonded together such that the single chips of thickness dl are sandwiched between the second wafer W2 and final carrier wafer CW. After producing this sandwich, the second wafer W2 is removed by de-bonding. Figure 6G shows the resulting structure .

In a last step the thickness of the single chips that are now re-bonded on the final carrier wafer CW are reduced in thickness by grinding, lapping and/or polishing to achieve a structure as shown in Figure 6H.

Figure 7 compares a partitioned thin film functional layer SLA produced on a standard carrier wafer CW1 in Figure 7A with a thin film functional layer SLA produced on a high precision carrier wafer CW2 depicted in Figure 7B. A standard carrier wafer CW1 is specified with a total thickness

variation (TTV) of 5 ym and less. High precision wafers with a TTV smaller than 1 ym are more expensive but still

achievable. Figure 7A shows a partitioned thin film

functional layer SLA according to Figure IE produced on a standard wafer as a carrier wafer CW1. After grinding and polishing, the total thickness variation of the carrier wafer CW1 transfers to the total thickness variation of the thin film functional layer SLA but with interchanged signs. At those points where the thickness of the carrier wafer is at a maximum d _max , the thickness of the functional layer is at a minimum d _min and vice versa. Hence, in a later electro

acoustic device manufactured from the functional layer, all device properties depending on the thickness are varying according to the total thickness variation of the functional layer .

In contrast thereto, Figure 7B shows the same arrangement when a high precision carrier wafer CW2 with a low total thickness variation is used. Such high precision wafers could be manufactured and selected if the manufacturing process thereof does not exclusively yield high precision wafers. On such a carrier wafer CW2 with a low total thickness

variation, the piezoelectric functional layer can be produced with the same low total thickness variation. Together with the process according to the third variant as shown in Figure 3, the total thickness variation of the piezoelectric layer can be minimized. If using a process according to the third variant as shown in Figure 3, the high precision wafer could be reused to save the relatively high costs of such a

selected wafer.

Figure 9 shows two functional wafers Wl, Wl' that comprise sections of a piezoelectric material. The sections of the functional wafer Wl may comprise the same material like the sections of the functional wafer Wl'. After singulation by dicing individual sections from the two wafers are

transferred and bonded to a carrier wafer CW. As a result, the carrier wafer CW e.g. of Si comprises sections of both wafers and has hence a greater wafer area than each of the functional wafers W1,W1'.

According to an embodiment, the two wafers Wl and Wl' differ in their piezoelectric material or in their crystallographic orientation. As a result, different sections of the different precursor wafers are bonded to the same carrier wafer and may be processed in parallel in further steps. It is clear, that sections of more than two precursor wafers may be bonded to the carrier wafer dependent on the relative sizes of

precursor wafer Wl and carrier wafer CW.

Figures 10A to IOC show different patterns of how chip sections CH and pieces P comprising more than one chip section CH of two differing wafers Wl can be arranged on the carrier wafer CW. Figure 10A depicts a checkerboard pattern of first and second different chip sections CHI, CH2

originating from two different precursor wafers W1,W1'. This means that in a horizontal row first and second chip sections CH1,CH2 are alternating. In each vertical column first and second chip sections are alternating too such that each row is shifted against the adjacent row. A first and an adjacent second chip sections CH1,CH2 form a virtual carrier chip section CCS. In the figure, only two such virtual carrier chip section CCS are marked with a thick-lined rectangular. Each carrier chip section CCS is assigned to a later chip area comprising two chip sections CH1,CH2 of different piezoelectric material or different crystallographic

orientation . Figure 10B shows a carrier wafer CW with the second

arrangement of first and second pieces P1,P2 each comprising a multitude of chip sections CH. The row of first chip sections form a first piece PI and a row of second chip sections CH form a second piece P2. Both pieces P1,P2 are arranged in an alternating sequence parallel to each other. The rows are dimensioned to cover a maximum amount of the carrier wafer CW such that a maximum number of chip sections CH is retrieved.

Figure 10C shows a third possible arrangement where first chip sections are arranged in two adjacent parallel rows or pieces P1,P2. Between two pairs of first rows PI two rows P2 of second chip sections are inserted such that carrier chip sections CCS are formed each comprising a first chip section CHI and an adjacent second chip section CH2. Of course it is possible that two neighbored rows of uniform chip sections CH may alternatively be formed as one piece P.

Figure 11 shows a carrier chip section CCS after singulation from an arrangement as shown in figure 9 or 10. The carrier chip section CCS comprises a first chip section CHI and a second chip section CH2 bonded to common piece of carrier wafer CW. An intermediate layer IL or layer stack may be arranged between a chip section CH and the carrier wafer CW for achieving enhanced bonding strength or for isolation or any other purpose. First and second chip section CHI and CH2 may comprise different piezoelectric materials, e.g. a piezoelectric material A in a first chip section CHI and a piezoelectric material B in a second chip section CH2. In the first chip section CHI a first functional device FD1 may be realized and a second functional device FD2 may be realized in the second chip section CH2. Possible combinations of first and second functional device FD1, FD2 may be

resonator/resonator belonging to a first and a second filter or BAW resonator/ (TF) SAW resonator belonging to a first and a second filter. Alternatively the two chip sections CH1,CH2 may comprise the same piezoelectric material but have

different crystal cuts and hence different crystallographic orientation. Then two resonators belonging to a first and a second filter respectively can be combined in one carrier chip section CCS.

In an alternative embodiment shown in Figure 12 only one type of chip sections or pieces with one type of chip sections are bonded to a carrier wafer CW in a pattern that leaves a respective free section of the carrier wafer CW of silicon adjacent to each bonded chip section CH. In this free surface section of the silicon carrier wafer CW a semiconductor circuit SD or semiconductor device SD may be formed before bonding or after bonding the chip sections CH or pieces P having chip sections thereto. The semiconductor device SD may be combined on the common carrier chip section CCS with the functional piezoelectric device FD1 in a functional way.

The new method has been explained with reference to a

restricted number of embodiments only. However the invention shall not be limited by the concrete embodiments and is only defined by the claims. The method is not limited to a

piezoelectric material as a functional layer. Each material that can be used as a thin film material in an electric device can be manufactured by the new method. This

combination may comprise a resonator of a filter and a semiconductor device SD which may be a switch or an

amp1ifier . Further, the method is not limited by any dimensions given by the embodiments. This refers to the size of the single chips as well as to the sections that are partitioned in the functional layer by the structuring lines. The thickness of the final thin film functional layer is also not restricted by the indicated dimensions that are optimized for

piezoelectric layers for thin film devices.

Moreover, it is possible to combine the first and fourth variants. Instead of using single chips CH, as shown in

Figure 4, larger pieces of a functional wafer can be

rearranged on a carrier wafer. These larger pieces can be provided with structuring lines before bonding them to the bonding surface of the second wafer. By the new method, wafers with a large diameter of 150 mm and more can be used as carrier wafers. This enables a production with a high number of electric devices in parallel on a single carrier wafer. Thereby the tolerances of the production process are minimized. Also the final dicing process is made simpler than a dicing process that has to be performed on a large area carrier wafer with an entire layer of a functional material arranged thereon. With the new method only one material has to be diced when singulating single devices from the carrier wafer. All these advantages result in a cost-efficient manufacturing process for wafers with a thin functional layer like a thin piezoelectric layer on top. List of used terms and reference symbols