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Title:
METHOD FOR PRODUCING THREE-DIMENSIONAL STRUCTURE, METHOD FOR PRODUCING VERTICAL TRANSISTOR, WAFER FOR VERTICAL TRANSISTOR, AND SUBSTRATE FOR VERTICAL TRANSISTOR
Document Type and Number:
WIPO Patent Application WO/2019/017326
Kind Code:
A1
Abstract:
[Problem] To provide a method for producing a three-dimensional structure, a method for producing a vertical transistor, a wafer for a vertical transistor, and a substrate for a vertical transistor, with which it is possible to suppress the release of Si by thermal treatment and make an interface between an oxide film and a core part consisting mainly of Si relatively smooth. [Solution] This three-dimensional structure is produced by: forming a three-dimensional shape by processing, by etching, a surface layer of a monocrystalline silicon substrate, the surface layer of which has an oxygen concentration of 1×1017 atoms/cm3 or greater; and then forming an oxide film on the surface of said three-dimensional shape by performing a thermal treatment. The three-dimensional structure has a shape having projections and recesses in the thickness direction of the silicon substrate, and the height thereof along the thickness direction of the silicon substrate is from 1 nm to 1000 nm, preferably from 1 nm to 100 nm.

Inventors:
KAMIJO KAZUTAKA (JP)
FUKUDA ETSUO (JP)
ISHIKAWA TAKASHI (JP)
IZUNOME KOJI (JP)
MIYASHITA MORIYA (JP)
SAKAMOTO TAKAO (JP)
ENDOH TETSUO (JP)
Application Number:
PCT/JP2018/026702
Publication Date:
January 24, 2019
Filing Date:
July 17, 2018
Export Citation:
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Assignee:
GLOBALWAFERS JAPAN CO LTD (JP)
UNIV TOHOKU (JP)
International Classes:
H01L21/336; H01L21/316; H01L29/78
Domestic Patent References:
WO2009096002A12009-08-06
Foreign References:
JPH08335668A1996-12-17
JP2008153530A2008-07-03
JP2009105227A2009-05-14
JP2010135592A2010-06-17
JPH03133121A1991-06-06
JP2011138955A2011-07-14
JP2004356314A2004-12-16
JPH04264776A1992-09-21
JP2010287739A2010-12-24
JP2001015504A2001-01-19
JP2001210869A2001-08-03
Attorney, Agent or Firm:
SUDA Atsushi et al. (JP)
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