FI ELD OF THE I NVENTI ON

5 The invention relates to a m ethod for optim izing electrical current in a DC link busbar of a power converter system , with a first and a second inverter bridge, connected to the DC link busbar.

BACKGROUND OF THE I NVENTION

Large power converters, especially AC/ DC and DC/ AC are becom ing an essential component in present day renewable energy production, in such as wind turbine generator and solar PV plant. At the sam e tim e, there is a still an important use of power converters in operations of electric motors in a m ore sustainable m anner, as variable speed operation is possible. I n order to operate efficiently, these5 power converters needs to have a low inductive DC link connecting the AC/ DC side with the DC/ AC side. To make the DC link in a low inductive design, they are m ost often designed in a lam inated plate design in either copper or alum inum .

This m eans that all the converted power has to go through the DC link, and thus the therm al stress on the DC link is high, as a high current has to pass through0 the lam inated busbar.

It is an object of the present invention to provide a m ethod and system which reduces the current in the DC link and thereby also the thermal stress, while still having the same operational range of the electrical machine connected. 5 SUMMARY

This sum m ary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This sum m ary is not intended to identify key features or essential features of the claimed subject m atter, nor is it intended to be used as an aid in determ ining the scope of the claim ed subject m atter.

I n an aspect, the present invention relates to a m ethod for optim izing electrical current in a DC link busbar of a power converter system , wherein the power

5 converter system com prises,

- a first inverter bridge, connected to the DC link busbar at a first end, the first inverter bridge having a first pulse width modulation signal and

- a second inverter bridge, connected to the DC link busbar at a second end, the second inverter bridge having a second pulse width modulation signal,

- measuring a current flowing in the DC link busbar from the first end to the second end,

- optim izing the current flowing in the DC link busbar by delaying the first pulse width modulation signal and the second pulse width modulation signal from each other with a carrier delay. 5 An advantage of the first aspect is mainly that current in the DC link busbar is optim ized and the converter will thereby be operated in m anner, where the losses in the DC link busbar is reduced, thus the temperature in the sam e, is m aintained within a safe range. Further advantages of the above are also a longer DC link busbar lifetim e and DC capacitor lifetime, and possible higher converter output. 0 According to one embodim ent of the invention the step of optim izing the current comprises m inim izing the m easured RMS current in the DC link busbar.

According to one embodim ent of the invention the step of optim izing the current further com prises, filtering the m easured current in a high pass filter, wherein the optim ization5 is based on the high pass filtered current measurem ent.

An advantage of the embodim ent is that is only requires optim izing of the harm onic com ponents.

According to one embodim ent of the invention the step of optim izing the current comprises, m inim izing the power losses in the DC link busbar by - deriving a m odel of the im pedance of the DC link bus,

- derive harm onic current com ponents of the current flowing in the DC link busbar,

- calculate power losses in the DC link bus based on the m odel of the impedance

5 of the DC link bus and the harm onic current com ponents.

An advantage of the embodim ent is that it only requires optim ization of the harmonic com ponents, and that it is the losses which are optim ized as the frequency component of the im pedance is taken into account.

According to one embodim ent of the invention the step of deriving at least one0 harm onic current components com prises:

- com ponents around the first harm onics of the switching frequency and

- com ponents around the second harmonics of the switching frequency.

An advantage of the embodim ent is that is only requires optim izing of the first and the second harmonic components, so the analytical part to derive the harmonics is reduced, and that it is the losses which are optim ized as the frequency component of the im pedance is taken into account.

According to one embodim ent of the invention the step of deriving at least one harm onic current components com prises:

- com ponents around the second harmonics of the switching frequency. 0 An advantage of the embodim ent is that is only requires optim izing of the second harmonic com ponents and that it is the losses which are optim ized as the frequency component of the im pedance is taken into account.

According to one embodim ent of the invention it further comprises,

- recording periodicaly data sets with carrier delay as a function of active power,5 reactive power and measured current,

- operating the converter system with a carrier delay based on look up tables in the data sets. According to one embodim ent of the invention the step of periodicaly recording data sets occurs with a fixed interval, such as once a day, once a week or once a m onth, and the carrier delay is updated with the same intervals.

According to one embodim ent of the invention step of periodicaly recording data

5 sets occurs based on predefined events, and the carrier delay is updated as a consequence of the prefined events.

An advantage of these embodim ent is that the system adapts to changes in parameters over tim e.

According to one embodim ent of the invention it further com prises,

- a first carrier frequency of the first pulse width m odulation signal and

- a second carrier frequency of the first pulse width modulation signal, wherein the first carrier frequency and the second carrier frequency are the sam e, or an integer m ultiply of one of the other.

According to one embodim ent of the invention it further com prises, 5 - a first carrier frequency of the first pulse width m odulation signal and

- a second carrier frequency of the first pulse width modulation signal, wherein the first carrier frequency and the second carrier frequency are different and a non-integer m ultiply of one of the other.

I n a second aspect, the present invention relates to a power converter with0 optim ized current flow in a DC link busbar, wherein the power converter system comprises,

- a first inverter bridge, connected to the DC link busbar at a first end, the first inverter bridge arranged with a first pulse width m odulation signal and

- a second inverter bridge, connected to the DC link busbar at a second end, the5 second inverter bridge arranged with a second pulse width m odulation signal,

- a sensor arranged to measure a current flowing in the DC link busbar from the first end to the second end, - a controller arranged optim izing/m inim izing the current flowing in the DC link busbar by delaying the first pulse width modulation signal and the second pulse width modulation signal from each other with a carrier delay.

I n a third aspect, the present invention relates to wind turbine with a power converter according to the first aspect and its em bodiments.

Many of the attendant features will be m ore readily appreciated as the same become better understood by reference to the following detailed description considered in connection with the accompanying drawings. The preferred features m ay be combined as appropriate, as would be apparent to a skilled person, and m ay be combined with any of the aspects of the invention.

Figures

Figure 1 , shows an exam ple of back to back power converter in a wind turbine application.

Figure 2, shows an example of a DC- Link model, with three LSC and three MSC m odules each.

Figure 3, shows PWM modulation by carrier com parison, showing two carriers.

Figure 4, shows enlarged view of two carriers with a carrier delay.

Figure 5, shows sim ulation of DC link current in converter with one gridside inverter and one generator side inverter as a function of carrier delay.

Figure 6, shows DC link stack currents.

Figure 7, shows sum of LSC currents and MSC current, and the LSC subtracted from MSC.

Figure 8, shows FFT spectrum of DC link stack currents.

Figure 9, shows a flowchart according the m ethod claim ed. DETAI LED DESCRI PTION

Figure 1 shows a wind turbine 100 (WTG) com prising a rotor 101 with at least one rotor blade 103, such as three blades. The rotor 101 is rotatable by action of the wind. The wind induced rotational energy of the rotor blades 103 is transferred via a shaft to the generator 1 10. Thus, the wind turbine 100 is capable of converting kinetic energy of the wind into mechanical energy by m eans of the rotor blades and, subsequently, into electric power by means of the generator 1 10. The generator is connected with a power converter which comprises a generator side converter MSC 120 and a line side converter LSC 140. The generator side converter MSC converts the generator AC power into DC power, the DC power is transferred to the line side converter LSC via a DC link 130, where the DC link comprises at least one capacitor 135. The line side converter LSC converts the DC power into an AC power for injection into the utility grid 160. The line side converter is often connected to the grid via a step up transform er 150, with is not required. The generator side converter 120 is controlled by MSC controller 121 which receives control inputs, such as, but not lim ited to, generator voltages and currents and rotational speed of the generator 1 10. The MSC controller sends control inputs to the generator side converter such as PWM signals 122. Sim ilarly is the line side converter 140 controlled by a LSC controller 141 , which also receives voltage and current signals 145 of the outputs of the line side converter, and the DC link voltage level 136 and the current flow 137 in the DC link busbar 130. The LSC controller sends control inputs to the line side converter LSC such as PWM signals 142.

The PWM signals of both the LSC and MSC controller are based on a PWM carrier signals, and is operated with switching frequency (fsw) in the kHz range, often a few kHz.

A given converter with a given physical DC link construction will contain a certain set of inductances and capacitances in the DC link construction. An example of such is shown in Figure 2.

Often both the LSC and MSC converter comprises one or more stacks. Where a stack means a converter bridge with the capability of converting a portion of the required power, such that a 5MW converter could com prise 4 LSC converter stack and 4 MSC converter stack, where each stack converts 1 .25MW of 3 phase AC to DC power or reverse. Each stack is connected to the DC link busbar.

The DC link busbar of a power converter system is known to the skilled person, as low inductance system with a positive and negative conductor assem bled in a lam inar m anner. The physical dim ension of the DC link busbar differs from the design to design, but a power converter in the range of 2-4 MW, is often assem bled in a cubicle arrangem ent with a length of 3-8 m eters, m eaning that the DC link busbar often extent through out all the cubicles or at least the m ajority of the cubicle elements.

Figure 2 shows an electrical model of an arrangement where 3 MSC stacks are aligned next to each and followed by 3 LSC stacks.

Each converter stack branch comprises a switch elem ent 210, also labelled LSC1 - 3 and MSC1 -3. I n parallel with the swith elem ent 210 is a series connection of an inductance L_c, DC, resistance R_c, DC and capacitance C_DC. The connection to DC link busbar results in additional “parasitic” com ponents, an inductance L LBB and a resistance R LBB. The connection from one converter stack branch to the next converter stack branch leads to further com ponents, an inductance L_Link,SS and a resistance R_Link,SS. Further converter stack branches can be m odelled by expanding the model.

The part of the DC link busbar which is between a line side converter LSC stack branch and generator side converter MSC stack branch, is denoted by the component inductance L Link, CC and resistance R_Link,CC.

This m eans that a given converter will have a specific optim um of one or m ore PWM carrier delay values, as the optim um is given by the set of im pedances in combination with the PWM signals. By using the an optim al PWM carrier delay, the DC link RMS current can be lowered com pared to no PWM carrier adjustm ents.

I n Figure 3, the PWM m odulation carriers are shown as the triangular wave. The is a sinusoidal curve 301 which is the signal to be m odulated. This is done by comparing it to one of the carrier signals 302, 303. PWM m odulation is known to the skilled person, and will not be explained further.

This triangular carrier can be the same for all stacks in the LSC or MSC converter, or the individual stacks of the converter can have its own carrier. I n an em bodim ent of the invention, the individual stacks in the LSC or MSC converter are operated with interleaved switching, so there is a carrier delay between each stacks. This m eans the optim ization for m inimzing the losses in the DC link becomes complex, but still possible.

Furtherm ore Figure 3 shows an exam ple of delayed carrier, grid side compared to generator side. Figure 4 shows in m ore details what is meant by carrier delay. With a zero degrees delays the LSC and MSC PWM carrier signals are aligned and in phase with each other. Whereas in Figure 4 there is delay between the two carrier signals shown by the arrow, from the solid line to the dotted line.

Going back to Figure 1 . Measurements of the DC link currents 137 in the DC side of the converter stacks are performed in order to analyze the losses in the DC link and analyze the frequency content of the current. Voltage m easurem ents 136 can also be used in the optim ization.

A current probe is mounted to measure the differential mode DC link ripple current for each stack. The DC current cannot easily be measured, because it is not “just” to insert a current sensor or current probe with a hall elem ent inside the DC link construction, due to the large physical dim ension of the lam inated DC bus.

I n an em bodim ent a rogowski probe can be inserted around the DC link where the converter stack DC term inals connect to the DC link busbar. I n order to m easure the higher harm onic com ponents in the current it is of course needed, that the current probe has a bandwidth which covers the frequency range of interest.

I n an em bodiment it is also possible to m easure the DC output current from each stack.

Figure 5 shows a sim ulation of DC link current in converter with one gridside inverter and one generator side inverter as a function of carrier delay. The results of this carrier delay sweap, shows especially around 0,2 and 0,3 times ( 1 /fsw) the RMS current drops to an interesting level of around 80% compared to if no PWM carrier delay is used.

Figure 6 shows DC side current m easurem ents of the three converter stack branches (upper Figure: Line side, lower Figure: machine side) without a carrier delay, where the legend mentions traces from the LSC A, LSC B and LSC C, i.e. stack A, B & C. and sim ilar for generator side MSC. The stack arrangement used, is with 3 MSC stacks aligned next to each and followed by 3 LSC stacks, sim ilar to the electrical m odel of Figure 2.

The RMS value of each m easured current is calculated. Results give that the outer stack has the highest RMS current, as expected and also seen in sim ulation, which is due to the fact that the outer stacks see the highest inductance in the DC link busbar.

Figure 7 shows measurem ents of the sum of all LSC DC side currents 701 and the sum of all MSC DC side currents 702. The sum of the LSC currents and the sum of the MSC currents are subtracted from each other 703 to make a check if this gives a zero or close to zero , which seem s to be the case.

The PWM carrier on the MSC side of the converter can be m oved in tim e compared to the LSC side, to see if the DC link current can be changed or lowered. The MSC side carrier is for exam ple delayed from 10 to 100 % of a switching tim e fundamental ( 1 /fsw) . To achieve the optimal current in the DC link busbar.

The optim ization of the current can be made sim ply by optim izing the RMS current. This can be done by calculating the RMS current of each converter stack for both the LSC and the MSC stack, and then find the average RMS current. The average RMS currents are the derived for a set of carrier delay values, and can then be optim ized. This was done for the sam e system as sim ulated in Figure 5, and the sim ulated and m easure optim um seem ed both to converge around 0.2 to 0.3 times 1 /fsw.

I n a more com plex manner the frequency com ponents in the current m easurem ents are included. Persons fam iliar with FFT analysis of PWM operated converters, knows that the FFT components are centered around side bands of the switch frequency (fsw) and 2* fsw.

I n each test point an FFT was calculated in Matlab to see what kind of frequencies that are changing during a change in the carrier delay. All the plots of the FFT analysis are analysed.

Figure 8 upper part shows an FFT plot of the LSC converter DC link current with a 0.3 carrier delay, currents are shown for all three stacks, the plots are very sim ilar from one stack to the other, and it therefore makes no sense to show three individual figures. Figure 8 lower part shows the sim ilar FFT plot of the MSC converter DC link current.

It was noted that the 2* fsw com ponent drops significantly around 0.3 delay.

The results show that the fsw and 3* fsw components only changes very little during the carrier delay sweep, however the 2* fsw com ponents are significantly changing and lowered around 0.2 and lowest at 0.3 which is also the point where the total RMS current is lowest.

The conductors of the DC link busbar have, as all other conductors, a frequency dependent im pedance. Thus to further im prove the capacity of the DC link busbar it is im portant to m inim ize the losses in the busbar, as it is the losses which courses the tem perature increase. Taking the frequency dependent im pedance into account when looking at the current spectrum of the DC link current, m eans that it m ay pay to have higher first harmonic current than a higher second harm onic current, as the im pedance is higher around the second harm onic. This m ay explain som e of the decrepansies between the calculated losses and m easured losses.

Based on the frequency analysis, the losses in the DC link can be calculated for each frequency. Results shows that the resistance increases with the frequency and that the inductance decrease with the frequency. The values are also influenced by the operating tem perature of the DC link busbar, in the sense that the resistance increases with the tem perature.

When the impedance and current are known for each frequency com ponent, the total losses in the DC link busbar com ing from the ripple current can be calculated.

It is also possible to break the DC link busbar in to lengthwise elem ents in respect of Figure 2. The calculated losses based on the measured currents are m uch higher than the sim ulated losses. Nevertheless to m easured and calculated results shows a m inim um in the losses around a carrier delay of 30% of the switching frequency fundamental, com pared with the losses in the nom inal setpoint.

Higher sosses in the DC link busbar m eans rise in tem perature of the m etal conductor, so any decrease in the losses means an avoided tem perature increase, with a potential to conduct a higher load. Results from a real implementation in a converter system of a multimegawatt system, shows that the losses in the DC link in can be reduced 65% and the DC link busbar temperature can be lowered from 67°C to 55 °C.

In conclusion, the current can be lowered by changing the PWM carrier position for the MSC side, compared to the LSC side, even with a simple current optim ization.

The frequency spectrum of the DC link current, often only have a few groups of harmonics, centered around the switching frequency, the first harmonic and the second harmonic of the switching frequency. It is therefore not needed to perform a full FFT (Fast Fourier Transformation) of the current, simple bandpass filtering of the current around both the first and the second harmonic is sufficient to optimize the losses in the busbar, as an estimate of the impedance at the specific harmonics can be used.

It is therefore possible to make an improved optimization where the optimization is based components around the first harmonics of the switching frequency and components around the second harmonics of the switching frequency. Optionally the DC component may also be used.

In a further embodiment the optimization is only performed based on the components around the second harmonics of the switching frequency.

In a measurement sequence the converter controller can sweep the PWM carrier delay from 0 to 100% of the switching frequency fundamental (1/fsw) with any number of internals n_interval each with a time length of t_step. n_interval can be any number, for example 10 or higher. If n interval is equal to 10 this means that the DC link current is measured at a carrier delay of

10,20,30,40,50,60,70,80,90 and 100% delay of the MSC carrier compared to LSC carrier.

In an embodiment, the delay is measured in counts, where the controller can decide to run the converter in the optimal point.

In an embodiment the carrier delay step are devided into a high number of steps, such as 100 or 1000 or higher. Based on the results a look up table can be generated with data, the controller will choose the optimal carrier delay and use that param eter. The carrier delay can be preset based on a preset load index, both active or reactive power based, in a m ore advanced and preferred embodim ent the optim ization of the carrier delay

5 runs routinely in the background, and thereby taking present load and status of the converter system into account, such as temperature and degradation of the DC link capacitors.

The following parameters will change the optim al operating point: Ugrid, Pgrid, Qgrid, Ude, Ugen, fgen, m odulation index and m odulation strategy. 0 It can therefore be beneficial to add extra dim ensions to the optim ization, which takes into account one or more variables from the list: Ugrid, Pgrid, Qgrid, Ude, Ugen, fgen, m odulation index and modulation strategy.

I n an em bodiment the controller periodicaly records data sets carrier delay as a function of active power, reactive power and m easured current, with a fixed interval, such as once a day, once a week or once a month, and the carrier delay is updated with the sam e intervals.

High load conditions m ay also alter the physical properties of specific com ponents in the power converter and thus make it relevant to adjust the data sets for which the optimal carrier delay is chosen. 0 I n an em bodim ent in the controller periodicaly records data sets based on predefined events, and the carrier delay is updated as a consequence of the prefined events.

I n an em bodim ent only two different carriers are used, one for the line side ( LSC) and one for the generator side (MSC) . 5 I n an em bodim ent each converter stack I section has its own carrier, and the optim ization becomes more com plex.

I n an em bodim ent the switching frequency of the both the m achine side inverter and the grid side inverter m ay not be the same.

Figure 9 shows a flow chart of the m ethod for optim izing electrical current in a DC0 link busbar of a power converter system , wherein the power converter system comprises, a first inverter bridge, connected to the DC link busbar at a first end, the first inverter bridge having a first pulse width modulation signal, and a second inverter bridge, connected to the DC link busbar at a second end, the second inverter bridge having a second pulse width m odulation signal, where step 910 is m easuring a current flowing in the DC link busbar from the first end to the second end, step 920 is optim izing the current flowing in the DC link busbar by delaying the first pulse width modulation signal and the second pulse width modulation signal from each other with a carrier delay.

Any range or device value given herein m ay be extended or altered without losing the effect sought, as will be apparent to the skilled person.

It will be understood that the benefits and advantages described above may relate to one em bodim ent or may relate to several em bodiments. It will further be understood that reference to 'an' item refer to one or more of those item s.

It will be understood that the above description of a preferred embodim ent is given by way of exam ple only and that various m odifications m ay be m ade by those skilled in the art. The above specification, examples and data provide a complete description of the structure and use of exemplary em bodiments of the invention. Although various embodim ents of the invention have been described above with a certain degree of particularity, or with reference to one or more individual embodim ents, those skilled in the art could m ake numerous alterations to the disclosed em bodiments without departing from the spirit or scope of this invention.