The invention concerns a method of regulating a digital phase-locked circuit, wherein an output signal from a voltage-controlled oscillator is locked to an input sig¬ nal, and wherein a predetermined mutual ratio of output signal frequency to input signal frequency is intended, and wherein the output signal is supplied to a counter which is latched periodically with a period determined by the input signal frequency, and the latched count is used for controlling the oscillator.

Regulation of phase-locked circuits of the above-men- tioned type is used e.g. in digital data transmission networks, which may be constructed as a synchronous digi ^¬ tal hierarchy consisting of a plurality of network ele ^¬ ments between which data may be transmitted.

When data are transferred in an SDH system, data are po¬ sitioned e.g. in a so-called STM-1 frame which consists of 270 columns with 9 bytes in each column. The first 9 columns in a frame contain overhead functions, frame lock, etc. A frame is transferred from one network ele- ment to another with a period of 125 μsec. This means that all bits in the frame, which are transmitted seri¬ ally, e.g. through an optical fibre, must have been transmitted after 125 μsec. For this to be feasible, the bits in an STM-1 frame must be transferred with 155.520 megabits per second.

Of course, it is important that the transfer rate of the complete frame and the timing of the transmission of the individual bits of the frame correspond closely to each other. In other words, it is important that the frame

transfer time of 125 μsec. and the bit read-out of 155.520 megabits per second are very accurate.

Therefore, it is desirable that the above-mentioned times are observed, and if this cannot be done, then to ensure that the bit read-out rate is closely bound up with the transfer time of the frame.

It is noted m this connection that the 125 μsec. are not controlled by a reference, but solely by a frequency de¬ rived from a transmission channel.

US Patent No. 4 864 253 discloses a phase-locked circuit which operates in the same manner as the method defined in the introductory portion of claim 1. An arithmetical unit is used to adjust the voltage-controlled oscillator, said unit calculating differences between successive counts for use when providing adjustment values for the voltage-controlled oscillator.

Now, the object of the invention is to provide a method, where the technical complexity is reduced so that the counter can provide adjustment values directly without further calculation units.

The object of the invention is achieved by a method of the type defined in the introductory portion of claim 1, which is characterized in that the counter currently counts up to a value which corresponds closely to the ra- tio of the output signal frequency to the input signal frequency. Hereby, a calculation unit deriving calcula¬ tions from successive counts may be omitted. It is noted in this connection that a predetermined count counted in a period corresponds to correct adjustment of the volt- age-controlled oscillator.

Expediently, the output signal of the counter circuit is transferred to a latch circuit and from there to a digi¬ tal compensation unit. This facilitates regulation in the loop, as counts both above and below a desired value may hereby be processed, without there being "jumps" from a high value to a low value.

For use m an SDH communications system, it is expedient that the output frequency of the voltage-controlled os- cillator is regulated to approximately 77.76 MHz and is locked to the input signal, which has a frequency of ap¬ proximately 8 kHz, and that the counter, whose maximum value corresponds to the ratio of the frequency of the output signal to that of the input signal, is latched to the value 4859 by correct phase locking.

The frame transfer time and the data read-out time are hereby locked to each other, as the ratio of 77.76 MHz to 8 kHz is precisely 9720.

It is noted in this connection that the frequency of the output signal is 77.76 MHz, as data may be read out on a positive as well as a negative flank of a pulse. With correct phase locking, the counter thus counts to 9720.

Expedient embodiments of the invention are defined m the dependent claims.

The invention will be explained more fully below with reference to the drawing, which shows an example of a digital phase-locked circuit of the invention.

In the drawing:

fig. 1 shows a digital phase-locked circuit for use m the method of the invention,

fig. 2 is a symbol diagram of how a counter counts pulses, while

fig. 3 symbolically shows how phase errors in the loop cause regulation pulses.

In fig. 1, the digital phase-locked loop is generally designated by 1, while 2 represents a fine-adjusting cir- cuit for the digital phase-locked circuit of the inven¬ tion, and 3 generally represents a circuit structure which is adapted to connect an internal frequency if the external frequency should drop out.

However, the circuits 2 and 3 form no part of the present invention and will therefore not be described more fully, as they are not important to the principles of the inven ^¬ tion.

In fig. 1, 4 represents a counter which receives an 8 kHz signal on its input I. An output signal is fed back from an output of a voltage-controlled oscillator 8 and is counted m the counter . The counter 4 counts the output signal periodically so that a count is latched m the latching circuit 14 e.g. m the middle of each period. The period is determined by the frequency of the input signal I . After each period, the latched value is trans¬ ferred to a digital compensation unit, which may expedi¬ ently be a subtraction unit 5 which subtracts half the maximum value of the counter from the count of the counter 4. For example, with correct locking between an output signal of 77.76 MHz and an input signal of 8 kHz, the counter may be arranged as a 14-bit counter which, m case of phase error 0, counts 9720 pulses during a period which is 120 μsec. The number then subtracted in the sub¬ traction unit is one half of 9720, which approximately

corresponds to 4859. The output signal from the compensa¬ tion unit 5 is supplied to an integrator 6, 9 which counts values from the unit 5 and transfer them to a digital-to-analog converter 7, which then provides a con- trol signal for the voltage-controlled oscillator 8 which then adjusts the frequency up or down.

As will be seen in fig. 2, this figure symbolically il¬ lustrates a typical development m the contents of the counter 4 as a function of time. The time axis in fig. 2 shows accumulated values as they may appear in the counter 4. At about 62.5 μsec., 187.5 μsec., etc., the entered values are latched.

Fig. 2 moreover shows a dashed line which symbolizes the value on the input of the digital compensation unit 5. Numbers just above or below 0 currently occur on the out¬ put of the compensation unit 5, cf. fig. 3.

Fig. 3 symbolically shows the surplus or deficit of counted pulses at point B, caused by the circumstance that the phase-locked loop is not locked properly. More particularly, the counter 4 will have counted too much or too little, and a little over 0 or a little under 0 will be counted on the output B of the compensation unit. De¬ pending upon whether the value is too high or too low, the voltage-controlled oscillator 8 will be regulated via the digital-to-analog converter 7 in accordance with the output signal from the compensation unit. The compensa- tion unit may e.g. be implemented as a subtraction cir¬ cuit .

While the invention has been explained preferably m con¬ nection with an SDH system, nothing prevents the invented phase-locked circuits from being used for many other ap-

plications where an output signal is to be locked to an input signal.