The present invention relates to satellite positioning, for example using the GPS and/or Galileo satellite networks among others and particularly to energy efficient methods of detecting and tracking signals from global navigation satellite systems. The invention is of value in among other things, smartphones, portable 'sat-navs' and in military systems including drones, communication systems, radars, sensors and tracking devices.

In known navigation satellite receivers, the receiver receives signals from a number of satellites, to determine position and time by. accurately measuring the timing of codes included in each signal, based on data on the time of transmission of those signals and the locations of those satellites. Data for satellite ephemeris and clock parameters is encoded into the transmitted signals . Using signals from several satellites of the same and potentially different constellations it is possible to reduce the error in the determination of position and time to very small values. .

Fig 3 shows a generalized GPS receiver architecture. Signal is taken in at L-band and passed through phases of amplification and down-conversion at R.F., I.F. and zero I.F. frequencies. At some point in the chain, the signal has to pass through an analogue to digital interface to allow the information to be taken into a digital processor. The digital processor is needed for navigation computations and signal control. As the code and carrier tracking loops are closed in software the processor would also provide the necessary feedback control signals.

There are a number of positions in the architecture in Fig 3 at which code and carrier residual plus Doppler injection can take place, at I.F., baseband analogue or baseband digital. It should be noted that all local oscillators in the R.F. and I.F. down-conversion chain and those in the generation of replica code and Doppler are part of the carrier loop and all must be aligned in phase from the same fundamental oscillator. Following the injection point in the receiver chain the circuit becomes dedicated to the reception of a signal from a particular satellite. Hence for the reception of signals from several satellites the circuitry after this point has to be duplicated by the number of satellites tracked or alternatively be time-shared that is cycled or multiplexed between them. In order to reduce circuit complexity system designers have pushed the injection point as far back in the chain as possible. This desire has led to code correlation and Doppler correction being performed in a digital process at or near baseband signals. There were good reasons for this as it solved the problems of leakage through mixers by the use of numeric multipliers, the problem of stabiljty and q-factors of the analogue filters at I.F. were a problem for an analogue correlator. In traditional digital implementations a satellite positioning receiver receives satellites' signals and down-converts them to a digital implementation. Typically the down-conversion process involves reception by an antenna, amplification and conditioning (filtering) and mixing the received signals with a locally generated signals generated from local oscillators to Intermediate Frequencies (IF). It should be noted that the satellite signals are many dBs below the thermal noise of the receiver and the processes described here are simply to condition the received signal before the demodulation process is commenced. It is important to carefully select the down-conversion frequencies. A two stage superheterodyne design is typically used to down-convert the received RF to an intermediate frequency that can be digitized. The IF can be at baseband signal usually with a where the mixer has generated Inphase and Quaderature components (that is offset by 90 degrees in phase). With advances in technology direct downconvertion to near baseband is possible. The signals are then digitized. When reduced to baseband Inphase and Quaderature (offset by 90 degrees in phase) the components are required to efficiently demodulate the signals.

Harmonics and local oscillator feedthrough that are potentially present in the mixer process must be removed through the frequency plan design, that includes the use of band pass filters at the IF and bandstop filters at the harmonic.

Conversion to baseband is the process of converting the IF signal to that of in-phase and quadrature components that are still modulated by the satellite Doppler. Most modern receivers do not convert to an absolute zero frequency but intentionally leave a residual offset before digitization (analogue to digital conversion).

In order to detect, acquire and track the signals the receiver generates two replicas of the received signals that are used in a correlation process offset by a phase different of 90 degrees, converts these to digital signals, and compares the two replica digital signals to the real digital signal. The expectation is that one of the comparators will generate a strong signal (after summation over a period of time), while the other will generate a weak or zero signal (again after summation). If this is not the case, then neither of the replica signals are accurately in phase with the real signal, and the ratio of the two signals is used to adjust the timing the two replica signals, so that one of them is then accurately in phase with the real signal. In this way, using continuous negative feedback, the relevant replica signal remains constantly locked in phase with the real signal.

The adjustment in timing of the replica code signal is controlled by a delay lock loop to ensure the rate at which the phase of that replica signal is maintained as there is always relative motion between the satellite and receiver (Doppler shift) due to orbit motion and ahy movement of the receiver, the amount of change indicates the relative position change. Satellite receiver technology has already made great advances in terms of the reduction of power required, however further advances are needed so that battery powered and portable receivers can operate for longer, or with a smaller battery.

The present invention aims to provide a means whereby the power consumption of satellite navigation receivers can be reduced compared with known methods.

According to an aspect of the present invention there is provided a method of determining the location of a satellite navigation receiver, having the steps of:

Receiving a first real satellite navigation signal (R) with a code, from a satellite in a navigation satellite system via a receiver, and downconverting it to reduce its carrier frequency;

Generating a first replica signal (Fl) representative of the real signal, and a second replica signal (F2) being the same as the first replica signal, but one code chip delayed such that they are substantially orthogonal with respect to each other;

Comparing R and Fl to generate a first comparison signal (CI) and integrating this over a period of time to generate a first output (01);

Comparing R and F2 to generate a second comparison signal (C2) and integrating this over a period of time to generate a second output (02);

Comparing 01 and 02 to measure a their power difference and adjusting the timing of Fl and F2 in concert, so as to maintain a predetermined ratio between 01 and 02;

Monitoring variations made to the timing of Fl and F2, to determine the relative movement of the receiver and satellite;

Providing an aligned replica signal at a predetermined phase relationship to at least the first replica signal, such that it is substantially non-orthogonal with the real signal, and mixing it with the real signal to remove the code on the received signal and leave the residual carrier signal plus any data that the real signal contains;

Performing the above steps for two additional real satellite signals from two additional respective satellites forming a constellation with the first, based on the residual carrier signal plus data on the motion of the satellites, and determining the location of the receiver;

Outputting the location of the receiver either to a user via a display to enable the user to know the location track a path or navigate a path, or to a machine to enable the machine to navigate a path or to inform a user; Wherein:

In the steps of Comparing R and Fl and of Comparing R and F2, the comparisons are performed using two respective Analogue Comparators, and CI and C2 are Analogue signals;

Each of the two Analogue Comparators is comprised in an Application Specific Integrated Circuit Radio Frequency Chip (ASIC RF Chip); and

The residual carrier signal is passed through an analogue to digital converter to generate a digital signal which is used in the step of determining the location of the receiver.

As just one A/D converter is needed downstream of a comparator, in place of the usual three A/D converters (upstream of the comparators), and this enables a reduction in power consumption. The use of analogue comparators would ordinarily be very problematic, expensive, bulky, unreliable and/or power hungry to the extent that it is an approach that would be strictly avoided by those in the art. This is because the parameters of each of each analogue comparator (e.g. gain) would need to be carefully tuned in view of the weakness of the satellite signal. However by implementing them on an ASIC chip the inventor has identified that these problem is avoided.

Determination of the location of the receiver using the digital signal is a process that is well known in the art and described in the literature, particularly regarding GPS recievers and is accordingly omitted for brevity. A wide range of further processing steps are possible as is known in the art, such as distinguishing between reflected signals in an indoor environment, determining motion based on Doppler shift, and various known methods for obtaining an initial lock on a satellite signal.

Preferably the two Analogue Comparators are comprised in the same ASIC RF chip. This has the advantage that fewer components are required. Preferably the step of mixing is performed using an Analogue Comparator, and preferably this third Analogue Comparator is comprised in the same ASIC RF chip as the first two Analogue Comparators. Preferably there are at least 6 analogue comparators (3 satellites x 2 comparators), more preferably at least 8 (4 satellites x 2 comparators), more preferable at least 9 (3 satellites x 3 comparators), and most preferably at least .12 (4 satellites x 3 comparators). Preferably all of these are comprised in the same ASIC RF chip.

Optionally the receiver is further provided with two digital comparators, arranged to receive signals from three analogue-to-digital converters, in turn arranged to receive the three signals R, Fl and F2 respectively, and the receiver switches between use of the analogue comparators and the digital comparators. With this approach the receiver can be switched between a normal and low power mode, for example using the low power mode only after achieving a lock on a satellite signal. I.e. the method is performed after signal acquisition process has completed, and during a position tracking process.

Preferably the integration time is in the range of 1 to 20 milliseconds in order that it is sufficiently long to enable the signal power to be above the noise, but sufficiently short such that any Doppler uncertainty will not corrupt the measurement. Longer integration times can also be used as is known in the art.

According to a second aspect of the present invention there is provided a satellite positioning receiver adapted to perform the method of any one of the preceding claims, and comprising two Analogue comparators each comprised in an ASIC.

Furthermore according to a third aspect of the present invention there is provided a satellite positioning receiver for determining its own location comprising:

Means for receiving a first real satellite navigation signal (R) with a code, from a satellite in a navigation satellite system via a receiver, and means for downconverting it to reduce its carrier frequency;

Means for generating a first replica signal (Fl) representative of the real signal, and a second replica signal (F2) being the same as the first replica signal, but one code chip delayed such that they are substantially orthogonal with respect to each other;

Means for comparing R and Fl to generate a first comparison signal (CI) and integrating this over a period of time to generate a first output (01);

Means for comparing R and F2 to generate a second comparison signal (C2) and integrating this over a period of time to generate a second output (02);

Means for comparing 01 and 02 to measure a their power difference and adjusting the timing of Fl and F2 in concert, so as to maintain a predetermined ratio between 01 and 02;

Means for monitoring variations made to the timing of Fl and F2, to determine the relative movement of the receiver and satellite;

Means for providing an aligned replica signal at a predetermined phase relationship to at least the first replica signal, such that it is substantially non-orthogonal with the real signal, and mixing it with the real signal to remove the code on the received signal and leave the residual carrier signal plus any data that the real signal contains; Means for determining the location of the receiver based on the residual carrier signal plus data on the motion of the satellites, and;

Means for outputting the location of the receiver either to a user via a display to enable the user to know the location track a path or navigate a path, or to a machine to enable the machine to navigate a path or to inform a user;

Two Analogue Comparators arranged to compare R and Fl and to compare R and F2 to produce CI and C2 respectively as analogue signals; and,

An analogue to digital converter arranged to receive the residual carrier signal to generate a digital signal for use by the means for determining the location of the receiver; and,

Where each of the two Analogue Comparators is comprised in an Application Specific Integrated Circuit Radio Frequency Chip (ASIC RF Chip).

Optionally the receiver is provided with two digital comparators, arranged to receive signals from three analogue-to-digital converters, in turn arranged to receive the three signals R, Fl and F2 respectively, and the receiver is adapted to switch between use of the analogue comparators (e.g. to operate at a lower power consumption) and the digital comparators (e.g. to maximize signal to noise ratio).

Optionally the receiver is configured such that the analogue comparators are in use after signal acquisition process has completed, and during a position tracking process. By using the analogue comparators during this phase the power consumption is reduced during this phase, which has greater impact when using satellite positioning constantly for an extended period, and for battery powered receivers greatly extends the battery life.

Typically the satellite positioning receiver is battery powered, i.e. comprising a battery arranged to power the rest of the satellite positioning receiver. The term battery encompasses fuel cells used as a substitutes for conventional solid batteries. Battery power and other sources of limited amounts of power are synergistic with the present invention which together can provide for a longer lasting or lighter weight receiver. Optionally the battery is a fuel cell. Alternatively or additionally, the satellite positioning receiver comprises an energy harvesting device. The energy harvesting device may be a solar cell, a thermoelectric generator, a device adapted to generate electrical energy from acceleration or vibration or shifting of weight such as caused by the movement of a wearer of the device. More generally, preferably the receiver is powered by a portable power source and is itself portable. Typically the receiver is a portable device and comprises a graphic display. Optionally the receiver is a GPS receiver, optionally it is a Galileo receiver, or optionally any other Global Navigation Satellite System or augmentation system receiver, and may be capable of switching between any or any combination of these signals (or optionally it may be capable of usingthem simultaneously).

Further, the receiver may be capable of any other functionality commonly associated with satellite receivers, such as providing directions, using other sources of information or other signals to help determine position, showing a location on a map etc.

According to a second aspect of the present invention there is provided a satellite positioning receiver adapted to perform the method of the first aspect, and comprising three or more Analogue comparators for each reception channel all comprised in an RF ASIC.

By ASIC RF Chip is meant an application specific integrated circuit radio frequency chip with a bespoke and tailored design for performing the analogue comparison described above. Comprised in an RF ASIC Chip means that the whole of the analogue comparator is arranged in one chip as opposed to being provided by a separately formed electronic components operating together. Generally when comparators are described as being on the same chip this may mean on parallel wafers of semiconductor material within a single component that is seated (typically via pins) upon a printed circuit board alongside other components, but preferably the comparators are comprised in a single contiguous element of semiconductor material. Typically the element of semiconductor material (and the ASIC RF Chip) has the sole purpose of performing analogue comparisons at radio frequencies, but optionally it comprises further etched elements such as a digital to analog comparator, or frequency converter etc.

The ASIC RF Chip needs to be accurately etched to ensure the parameters of the analogue comparators are correct, else the analogue comparators must include adjustment means to adjust these parameters. According to one embodiment the (each) analogue comparator is a composite analogue comparator comprising, for example, three sub-parts, each being of different sizes or gains or other parameters, for example in the ratio 1, 2 and 4 or 1, 2, 10, such that by selecting which combination of sub-parts are operated in parallel, the properties of the whole can be tuned to the required levels to a known level of accuracy, so as to compensate for variations introduced during manufacture. Alternatively, as Analogue ASIC Chips are becoming increasingly evenly manufactured and analog comparators on such Chips can be produced with less variation than in the past, this approach (or any others to compensate for variations) can advantageously be avoided. To determine position in three dimensions it is necessary to either track four satellites (that must be angularly dispersed from one another from the point of view of the receiver, as well as being above the horizon) however it is also possible to use just three satellites provided that the receiver comprises an accurate clock or has access to information from one. As it is possible to use satellite signal (usually at least four) to accurately determine the time (Usually in addition to the location).

The 'location' typically includes at least location in space (generally in three spatial dimensions), optionally at least temporal location (location in time),, and includes typically both but optionally may be limited to just location in space.

By substantially non-orthogonal is meant that the aligned replica signal is sufficiently close to being in phase or in antiphase with the real signal that mixing of them generates an acceptable output for digital conversion and further processing. This might conceivably be 45 degrees apart (i.e. so that only two replica signals are needed) but preferably these two signals are fully aligned, being either in phase or antiphase.

While the invention has been described with regard to tracking one satellite signal, normally the receiver will track several signals, having multiple pairs of analogue comparators, each pair for use with a different satellite signal (and preferably at least three pairs for at least three signals). This enables the receiver to determine its position in three dimensions based on signals from three suitably spaced satellites.

The invention will now be described with reference to the following figures in which:

Figure 1 illustrates the operation of a known satellite positioning receiver, and

Figure 2 illustrates the operation of a satellite positioning receiver according to a first embodiment of the present invention.

Figure 3 shows a circuit diagram for conversion from L-band to baseband and conversion to digital.

Figure 4 illustrate the operation of a satellite positioning receiver according to a second embodiment of the present invention.

A known satellite positioning receiver as illustrated in Figure 1 receives a real satellite signal (R) from a satellite and creates two replica signals with a frequency and waveform of that which is expected from the satellite (i.e. in the case of use with GPS, the real signal is a GPS signal, and the replica signals have wavelength and waveform according to that defined in the GPS standard). Preferably a signal acquisition process has already been performed as is known in the art, in which case it is possible for the replica signal to have substantially the same data at substantially the same timing as the real signal does.

The three signals are converted (A/D) to digital format via analogue-to-digital converters into three digital signals. The real (digital) signal is compared to each of the replica (digital) signals via two digital comparators (D) to produce two digital outputs. Each of these are repeatedly summed (∑) over a predetermined period of time , (or to produce a time average if preferred) to produce two output levels. These are compared to determine whether a preselected one of the replica signals (Fl) is in phase with the real signal (R). By arranging the two replica signals out of phase, preferably orthogonal, when the selected replica signal (Fl) is in phase with the real signal (R) then the output of the comparator produced from the other replica signal (F2) should be zero. By monitoring the two outputs the timing of the replica signals (Fl, F2) can be varied in tandem so as to maintain the selected replica signal Fl in phase with the real signal.

The amount of variation in the timing of the predetermined replica signal is monitored (not shown) and the total net variation is indicative of the variation in distance between the receiver and satellite as is known in the art. Coupled with data on the motion of the satellite, which may be obtained periodically from data in the satellite sjgnal as is known in the art, changes in the position of the receiver can be monitored. This example is given with respect to one dimension and one satellite signal. By applying the above method to three, or more satellite signals changes in position of the receiver in three dimensions can be monitored as in known in the art. This may be output via a portable graphical display (not shown) such as a smartphone, or to a user or machine such as an autonomous vehicle.

It should be noted that although figure 1 shows the two integration outputs being respectively maximized and minimized, it would be more normal to maintain them at equal levels, with the two replica signals having a phases relationship of +45 degrees and -45 degrees with respect to the real signal. This generally requires a third replica signal to be provided that is in phase with the real signal, for mixing with the real signal and generating an output for further analysis.

A satellite positioning receiver according to one embodiment of the present invention is illustrated in figure 2. Some of the processing steps shown match those in figure 1, however instead of converting the three signals (R, Fl, F2) to digital signals prior to comparison, two analogue comparators (A) are used to compare the real signal (R) with each of the replica signals (Fl, F2). The analogue comparators (A) each produce an analogue comparison signal (CI, C2). The comparison signals are summed (∑) to produce two outputs (0). The summation is either completed repeatedly over respective periods of time, or continually so as to produce a varying time average. The two outputs are monitored, and negative feedback applied to the timing of the two replica signals (top arrow) so as to maintain a constant power relationship between them and the real signal (R). A third replica signal centered between Fl and F2 is now in phase with the real signal.

By maintaining the replica signals (Fl and F2) so the third is in-phase relationship with the real signal, the output of the comparison of that signal and the real signal can be converted to a digital signal (A/D) via an analogue to digital converter, and then used for further analysis of the satellite signal timing or data as is known in the art.

As in the prior art method, the variation in timing of the replica signals (performed as necessary to maintain them at a constant phase relationship with the real signal) is monitored. This variation is used to determine the relative motion between the satellite and receiver, which, combined with data on the motion of the satellite is used to determine the motion of the receiver in one dimension.

More generally four or more satellite signals may be monitored, each using the method described above and by comparing four replica signals with four real signals, then based on data on the motion of four respective suitably spaced satellites, the motion of the receiver can be determined in three dimensions and time as is well known in the art (for example the method commonly used in GPS receivers).

A satellite positioning receiver according to a second embodiment of the present invention is illustrated in figure 4. Many of the features are similar to those shown in figure 2 however the Comparison is performed to evaluate whether the integrated outputs 01 and 02 are equal. If they are not equal the timing of the replica signals Fl and F2 (and also F3) are adjusted to rectify this, by means of a negative feedback loop.

Holding 01 and 02 equal is technically more straightforward than holding one at maximum and one at zero. The ratio of the two informs whether the replica signals are equally spaced either side (45 degrees phase offset) of the real signal, whether they are no longer equally spaced either side, and in which direction they have moved. However, as neither 01 nor 02 is a maximized output it is desirable (not essential) to provide a third replica signal F3 that is equispaced between Fl and F2 and which, provided the negative feedback loop operates correctly, will always be in phase with the real signal. By mixing the real signal with F3 (also a comparison step) preferably via a third analogue comparator, the (downconverted) carrier wave signal is captured with the code. Preferably the first and second outputs (01 and 02) are maintained at equal power by the comparison, and the first and second replica signals are maintained with a 45 degree phase difference respectively ahead and behind the real signal. This is the most technically straightforward approach. Similarly, the aligned replica signal preferably is a third replica signal having a phase equispaced between the first and second replica signals so as to be non-orthogonal with the real signal. This gives a comparatively strong clear signal for digital conversion and further processing according to various methods known in the art.

As the real signal has a phase modulated code, and the replica signal has the same code (indeed all of them do), upon mixing the two the code remains clearly present as phase modulation upon the carrier frequency.

The output of the mixer preferably is converted directly to digital (rather than being first integrated) for Doppler analysis and other steps as are known in the art.

As with the second embodiment shown in figure 2 only one signal associated with a particular satellite needs to be converted to digital, and this enables a reduction in power consumption to be achieved.

Correlation Estimate

The correlation processor requires a minimum of two inputs - one for the received signal samples and a second for the input of the corresponding receiver-generated replica samples. Optionally, a third input can also be used whereby the replica samples are provided in a baseband form with the third input having a corresponding set of samples of the residual carrier replica (sine and cosine functions in the equations). This first stage of processing performs the multiplication.

In a second step, the results of each multiplication are summed typically by an adder. Such summation can be performed either in parallel or in serial format, depending upon the design performance required, or a combination of the two - parallel and serial summation.

In modern Digital Signal Processors (DSP) implementations of the correlation process, the received signals are digitised prior to processing by complex multi-level digital circuitry. This has been a consequence of the extensive use of digital signal processing. However, optionally the application of analogue addition as a means to simplify the processing complexity. Apart from the simplification, there are other advantages to the analogue processing which are realised when high levels of interference are present at the GNSS receiver's input. These increase the dynamic range of the signal which has to be processed so that a large number of levels are required of the analogue to digital converter (ADC) in a digital receiver. This adds greatly to the receiver complexity when typically, a digital signal representation of 14 bits or more is required.

Generally there is means to perform the both the multiplication step and the addition step.

Multiplication Function

A digital signal processor's function is generally performed with a series of digital multipliers. In the case ith a requirement for a single multiplier, the received signal (after amplification, filtering, down-conversion and digitisation) is input to one of two inputs. The second input to the multiplier is connected to a source of the digital representation of a replica signal (to the one sought in the received signal). The replica signal contains both a representation of the spreading code and the residual intermediate frequency. This implies that the replica is formed through the process of multiplication of the baseband spreading code and an in-phase and/or quadrature digital representation of the residual intermediate frequency carrier.

A known alternative is that the two multipliers processes the signal one after the other in a serial arrangement. There are several means to fabricate ,these circuits on a silicon substrate, such as a multi-input series of exclusive-OR gates or as a full digital multiplier circuit. An alternative circuit is based on the use of the known Gilbert cell. The Gilbert cell is able to perform in either analogue or digital modes using either small signal or saturated signal modes.

A new circuit structure is proposed whereby the original Gilbert cell with two inputs is enhanced by the addition of a third multiplier input so that it performs the function:

S _mt (t) = a{t) b(t) - c(t) where the inputs are the time functions a(t), b(t) and c(t) resulting in the output signal Sout(t). Any of the inputs may operate in either analogue or digital modes. This optional behaviour is entirely due to the magnitude of the applied signal. The digital mode operates when the input signal (between two bases of any of the long tailed pair) is sufficient to ensure that all of the current available at the relevant emitters passes only though one of the transistor paths. For input signals with peak magnitudes less than lOOmv, the transistors operate in a linear mode.

Addition Function (Summation)

In prior art receivers, the addition function associated with the correlation process has been exclusively performed by digital signal processing using, for example, up-down counters, adder networks or logic arrays. The complexity of these is related to the number of bits represented in the signal and replica, and the number of summations required. If the signal is represented in 12 bits and the replica in 8 bits, the product of signal and replica is a number represented in 20 bits. For partial correlation intervals of, say, 1 ms at a sample rate of 32 Ms/s (= 215 samples per ms), the count accumulated in each ms interval can be as large as 35 bits. The complexity of the DSP networks is significant and generally not required for the received noise level. Prior art receivers have mitigated the width of the representation by circuits which reduce the number of bits in the representation (say to 15) prior to further processing. Such circuits are often adaptable to the signal and noise levels so that no significant precision is lost.

The alternative means of performing the summation proposed is the use of analogue techniques whereby the currents from each output of the enhanced Gilbert cells (EGC) are added together in a current summing junction. Such circuitry does not have the precision of DSP. The precision is limited by the variation of the value of the tail current in each EGC. The variations would be difficult to control in discrete component implementations of the circuitry. This is not the case for integrated circuit fabrications where the current variations can be maintained to within a band of 1% width. In this case the current variations appear as an additive noise to the signal, replica and intermediate frequency product. The circuit noise is reduced through the process of averaging so that, in practice, the additional circuit noise is not a significant factor.