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Title:
METHOD OF SETTING BACK BIAS OF MOS CIRCUIT, AND MOS INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2000/045437
Kind Code:
A1
Abstract:
A MOS circuit includes a plurality of MOSFETs to form a digital circuit. An input signal is supplied to the digital circuit, and a first back bias is applied to the MOSFET substrate or a well region so that a forward voltage may appear across the pn junction between the substrate or well region and the source region. When an input signal at a fixed level is applied to the digital circuit to disable the circuit operation, a second back bias is applied to the MOSFET substrate or well region so that a backward voltage may appear across the pn junction between the substrate or well region and the source region.

Inventors:
Kubo, Masaharu (Hitachi, Ltd. Semi-conductor & Integrated Circuits Division 20-1, Josuihoncho 5-chome Kodaira-shi Tokyo, 187-8588, JP)
Hiraki, Mitsuru (Hitachi, Ltd. Semi-conductor & Integrated Circuits Division 20-1, Josuihoncho 5-chome Kodaira-shi Tokyo, 187-8588, JP)
Mizuno, Hiroyuki (Hitachi, Ltd. Central Research Laboratory 280, Higashikoigakubo 1-chome Kokubungi-shi Tokyo, 185-8601, JP)
Ikeda, Syuji (Hitachi, Ltd. Semi-conductor & Integrated Circuits Division 20-1, Josuihoncho 5-chome Kodaira-shi Tokyo, 187-8588, JP)
Application Number:
PCT/JP1999/007034
Publication Date:
August 03, 2000
Filing Date:
December 15, 1999
Export Citation:
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Assignee:
HITACHI, LTD. (6 Kanda Surugadai 4-chome Chiyoda-ku Tokyo, 101-8010, JP)
Kubo, Masaharu (Hitachi, Ltd. Semi-conductor & Integrated Circuits Division 20-1, Josuihoncho 5-chome Kodaira-shi Tokyo, 187-8588, JP)
Hiraki, Mitsuru (Hitachi, Ltd. Semi-conductor & Integrated Circuits Division 20-1, Josuihoncho 5-chome Kodaira-shi Tokyo, 187-8588, JP)
Mizuno, Hiroyuki (Hitachi, Ltd. Central Research Laboratory 280, Higashikoigakubo 1-chome Kokubungi-shi Tokyo, 185-8601, JP)
Ikeda, Syuji (Hitachi, Ltd. Semi-conductor & Integrated Circuits Division 20-1, Josuihoncho 5-chome Kodaira-shi Tokyo, 187-8588, JP)
International Classes:
H01L21/761; H01L27/092; H01L27/12; H03K3/356; (IPC1-7): H01L27/092
Foreign References:
US5583457A1996-12-10
US5838047A1998-11-17
JPH09214321A1997-08-15
EP0594162A11994-04-27
JPH0621443A1994-01-28
JPH0936246A1997-02-07
US5659517A1997-08-19
JPH10189883A1998-07-21
JPH0418762A1992-01-22
US5814899A1998-09-29
Other References:
IEEE 1992 Symposium on VLSI Technology, Digest of Technical Papers, (1992), pages 104-105, XP002924341.
IEEE 1985 International Solid-State Circuits Conference, Digest of Technical Papers, (1985), pages 254-255, XP002924342.
Attorney, Agent or Firm:
Tokuwaka, Kousei (16-8, Inokashira 5-chome Mitaka-shi Tokyo, 181-0001, JP)
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