Title:
METHOD FOR SHIELDING MAIN BIT LINE FOR REFERENCE CELL
Document Type and Number:
WIPO Patent Application WO/2011/155120
Kind Code:
A1
Abstract:
A dummy main bit line (MBLD1) is arranged between a reference main bit line (MBLR1) and a core main bit line group (MBL1 to MBLj). A selection transistor (SLD1) provided between a sub bit line (BLD1) connected to a cell (31), and the main bit line (MBLD1) can be switched between a conductive state and a non-conductive state, independently from other selection transistors. The dummy main bit line (MBLD1) can be set to a ground potential by a shield grounding means (DTD1, 106) and can be used as a shield line for the reference main bit line (MBLR1).
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Inventors:
UEDA, Takanori (())
上田孝典 (())
NAKAYAMA, Masayoshi (())
上田孝典 (())
NAKAYAMA, Masayoshi (())
Application Number:
JP2011/002633
Publication Date:
December 15, 2011
Filing Date:
May 11, 2011
Export Citation:
Assignee:
PANASONIC CORPORATION (1006, Oaza Kadoma Kadoma-sh, Osaka 01, 〒5718501, JP)
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
UEDA, Takanori (())
上田孝典 (())
パナソニック株式会社 (〒01 大阪府門真市大字門真１００６番地 Osaka, 〒5718501, JP)
UEDA, Takanori (())
上田孝典 (())
International Classes:
G11C16/06; G11C16/04
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (Osaka-Marubeni Bldg, 5-7Hommachi 2-chome, Chuo-ku, Osaka-sh, Osaka 53, 〒5410053, JP)
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Claims:
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