The present invention can be applied instead of any traditional data transmis- sion protocol, such as CAN-protocol, in Intelligent Wiring Systems (IWS) for vehicles, such as described in the applicants patent applications WO 99/25585, WO 99/25586, WO 99/26331, WO 95/15594, WO 97/4901 and PCT/F198/00710. Of course, the invention can be applied also in intelligent wiring systems for building automation in homes and offices.

In the prior art methods and systems a number of successive signal states"1" or"0"is used to represent the desired binary value data. The ordinary bit-wise transfer of data messages is sensitive to EMI-interference which is one of the main problems in implementations of data transmission systems for automotive industry. Another problem is overcrowded data bus when data collision must be prevented in a system wherein several tens of intelligent load supply terminals (intelligent nodes) must communicate with each other and/or with a central control unit via a data bus.

It is prior known from patent specification US-4,429,384 a communication sys- tem for the transmission of digital information over a bus channel using pulses having a considerably different pulse length for the transmission of"0"and"1" bits, respectively. In this prior art the message is based also on successive signal states"1"and"0"to be separated from each other and therefore this system suffers from the same problems as described above.

The object of the present invention is to achieve an improved method for data transmission such that the above mentioned problems can be substantially reduced.

This object can be achieved by a method according to the features of claim 1.

The object can also be achieved by a system according to the features of claim 14.

In the following the preferred embodiments of the invention will be illustrated in more detail by reference to the enclose drawings wherein Fig. 1 shows an example of a data bit quartet composed transferred by the method of modulating the time delay between successive transitions; Fig. 2 shows an example of a message sent by several data bit quartets in packet format, each bit quartet being composed according to the prin- ciple of Fig. 1; Fig. 3 shows an example of a part of an Intelligent wiring system (IWS) wherein the new method for data transmission can be advantageously applied.

Fig. 4 shows an example of a message composed of several transition delay modulated bit quartets according to the principe of Fig. 1, the mes- sage being planned to be applied in the system part according to Fig.

3.

Fig. 5 shows an example of a driver unit (transceiver) operating under the new IWS protocol.

Physical media and device (Fig. 3 and Fig. 5) Unshielded, floating, differential two wire mixed topology data transmission cable without termination maser junction unit with an independent line condition supervisory circuit for both data wires.

Slew rate limited push-pull complementary output transmitters with high im- pedance state Differential analog receivers with anti alias filter and window discriminator * Digital signal conditioner for received analog signal At the end of the specification the transceiver device is explained in more detail with reference to Fig. 5.

Modulation method (Fig. 1) IWS data transfer is based on pulse width modulation of bit quartets. Each quartet contains or represents four data bits. The binary value of each quartet is used to adjust the delay between successive output transitions. A receiver measures delays between transitions and converts them back to the original data.

This modulation method generates less transitions and less EMI-interference than ordinary bit-wise transfer methods when sending random data at the same average bit rate, because every transition in signal path can transfer one quar- tet (four bits) of data.

Transitions (Figures 1,2 and 4) The modulation method depends on signal transitions instead of signal states.

There is no high/low or dominant/recessive states or bits as needed for prior data transportation implementations for automotive industry. A transition in the IWS (Intelligent Wiring System) cable is signale by complementing the electric charge of signal wires and then leaving the new state of electric charge pas- sively or using only a weak output driver to maintain the signal state in the cable.

Synchronization (Figures 1,2 and 4) A special synchronization pattern is used to find the start and the end of each data frame. The synchronization pattern contains two successive transitions.

The time delay between synchronization transitions is one transmit clock cycle.

Because all other quartets and heart beat signals have longer delay between transitions no transmitted signal can interfere with the synchronization signal.

This signal is possible to insert and detect at any time during the data transfer.

Every synchronization pattern starts a new data frame reception.

Supervisory When no data transmission is needed, the charge of signal wires is refreshed by a special heartbeat signal. Every unit is responsible for generating the heartbeat signal at specified periods.

The heartbeat signal is also used for detecting the condition of the transmission line. If, for some reason, the heart beat signal does not work in proper way the supervisory system can immediately alert the user about the damage and change the data transmission protocol into emergency mode.

In the emergency mode the transmission speed is slower and data transmitters does not work in complementary mode as normally. Transitions in emergency mode are energy pulses instead of alternating charges.

The master junction unit disconnects all data lines which can not generate proper heartbeat signals to get the rest of the system to working condition.

All supervisory elements are doubled independently. Every single data cable fault will be detected and corrected without major functional disadvantages.

Collision prevention If two (or more) transmitters decide to send a transition exactly at the same or

almost at the same time, the result will always be a single transition because both transmitters set the same new electric charge to the signal cable to gener- ate a new and exactly same type of transition.

A transmitter is not allowed to send a new transition immediately after detection of a new transition. This safeguard delay prevents the possibility that two or more transmitters could simultaneously set different charges to the signal cable and cause a true collision situation.

Due to presented method there is no possibility for collision of two or more transmitters. Instead, every transmitter have an opportunity to send new transi- tions without a risk of signal contamination to unpredictable state.

Bus arbitration Any transmitter can start transmitting when it detects the synchronization sig- nal. In the case, that there is no active transmissions running, the transmitter can start transmitting of a new synchronization signal itself.

When an active transmitter detects at any time an extra transition in the signal cable, it should stop transmission immediately. This happens normally during the first quartets of the data packet. The transmitter, which have shorter quar- tet, sends the transition of the quartet earlier than transmitters with a longer message. The transmitter with the shorter message quartet can continue with- out interruption and the transmitter with the longer message quartet gives up.

The extra transition situation may also happen when a very high priority trans- mitter breaks a transmission of a low priority transmitter by sending a new synchronization pattern in the middle of the low priority data frame.

Transmit signal timing (Fig. 1) Transmit signal timing is depending on chosen transmit clock frequency. This frequency sets the step value for transmitter delay unit. The shortest delay of one transmit clock is reserved for the synchronization signal. Multiple of trans-

mit clock cycles are used to send transitions for data quartets. Two cycles are used for the first binary data value 0000 (=0) and three cycles are used for the next binary data value 0001 (=1)... Finally 17 transmit clock cycles delay be- fore the ending transition of the quartet is used for the largest binary data value 1111 (=15). Any longer delay between transitions means heart beat and bus idle state.

Receive signal timing The receiver uses a receive clock frequency which is a multiple of the transmit signal frequency. This allows the receiver to measure the delay between transi- tions more precisely and to perform a digital signal conditioning before actual reception of the transition event.

After a reception of a transition, the receiver evaluates the time delay value measured from the last successive transition and decides how to translate the received time information. Only narrow time windows are allowed for possible data quartets. Between allowed signal width windows there is a fail safe areas for detecting incorrect random transitions. If the measured delay value is not belonged to any allowed signal windows, it is discarded by the receiver. This procedure prevents efficiently a random signal pattern to be accidentally re- ceived as a valid data packet.

If a receiver detects an illegal transition when it is actively receiving a message, it may generate an extra synchronization signal to break this transmission and to start the retransmission immediately.

IWS message format (Figures 2 and 4) All messages have same basic format. 32 data bits delivered either to all re- ceivers or to a single receiver with an acknowledge. All unused bit space (zero value quartets) will be spontaneously optimized to the shortest length during the modulation.

A message contains following parts: Synchronization from the transmitting unit Priority selection field 'Data fie ! d (8/32 bits) 'Error check field Synchronization from the transmitting unit Acknowledge field Synchronization from the receiving unit Priority selection field (Figures 2 and 4) This part of the message starts from the synchronization signal of the previous message or a new synchronization signal generated by the transmitter itself. All active transmitters may then start transmitting of message priority selection quartet. Possible values for the priority quartet are from 1 to 15. Zero value is reserved for acknowledge field. Many transmitters may have the same mes- sage priority. All transmitters start sending of their messages simultaneously.

During the transmission any transmitter trying to send a longer message quar- tet than others will be efficiently eliminated due to collision prevention mecha- nism. At the end of the packet only one transmitter should be actively transmit- ting.

In the special case that more than one message have exactly the same ad dress and data fields then all these messages will be properly delivered at the same time.

Target address field (Figures 2 and 4) This part of the message contains two quartets which uniquely selects the receiver for the message. If both target quartets have zero value then every receiver should receive a broadcast message. All receivers must have an unique pair of address quartets. This limits the maximum number of receivers to 255 units leaving one address for the broadcast.

Data field (Figures 1,2 and 4) This part of the message contains eight quartets used for actual data. Maxi- mum data bits in one message packet is 32-bits. Unused space will be spontaneously optimized to the shortest length during the modulation.

Error check code field (Figures 2 and 4) This part of the message contains two quartets representing a 8-bit ECC value calculated from the target address field and the data field. The error check can detect unusual errors passed from other error checking procedures.

Acknowledge field (Figures 2 and 4) This part of the message contains three quartets followed by a synchronization pattern sent by the receiver of the message. The first quartet is zero and next two quartets contains the address of the acknowledging receiver.

If any of these transitions are missing the transmitter should immediately send a new synchronization signal to restart transmitting of the message. If no cor- rect acknowledge has received after three retries the transmitter should delay the message and try again later. Messages which are addressed to every re- ceiver are not acknowledged.

Error checking Quality of the received signal timing is checked during the reception. This qual- ity detection is important to prevent a random noise signal to be recognized to a valid message. No error checking methods used for short messages is reliable enough to withstand a pure random signal without the signal quality check.

When transmitting a message the transmitter compares the transmitted signal to received signal. If there is any difference between those two signals the transmitter stops sending the message before it will be received.

When receiving a message the receiver checks the ECC code from the end of the data packet to confirm that the contents is logically correct and not messed up during the transmission.

All these precautions are made to confirm that no message could be acciden tally recognized in wrong way due to noise or interference in the IWS cabling.

In the case that some special signal needs a very special care for error detec- tion the signal can be selected to contain a bit pattern which is not near to any other used bit pattern. This way the probability of accidental reception of this specially selected signal is highly decreased.

Example of system for application the method The system according to Fig. 3 inclues IWS (intelligent Wiring System) cable which includes two wires for power supply and two wires for data bus. There may be several cable branches, each starting from a master junction unit, which is optional and may be replaced by a ring cable for connecting the cable branches with each other. The block of master junction units is in data communication with adaptation and monitoring block, through which any external programming of the system can be made, which monitors the"heart beat"and fault messages from the system and which controls the on-line dis- play to show the use the status of the system. Each cable branch has been provided by several intelligent sockets, which control the power supply from the IWS-cable to various loads, such as trunk light L1, in response to various in- puts, such as closing the trunk hatch switch S1, from any socket of the system.

The number of sockets in the whole system for vehicle implementation, for instance, is typically between 30-50, but may vary substantially depending on the application (e. g. in busses, ships, homes and offices).

The operation of system part of Fig. 3 takes place in view of Fig. 4 according to following steps: -Trunk hatch opens and closes the trunk light switch S1 -Input pin 11 connects to the ground and wakes up the CPU of socket 11 -Socket 11 starts evaluating the new input signal using the virtual schematics of the vehicle stored in the flash memory of the socket -Socket 11 founds that it does not have all information about the wiring of this signal number 51 -Socket 11 sends a priority class 4 message to socket 10 about virtual connection number 51 which has changed to 1 (unused data fields are 00000) -Socket 10 receives the message and checks the error check code 5220 -Socket 10 acknowledges by inserting an OK message after successful receiving of the message from socket 11 -Socket 10 starts evaluating the new input message using the virtual schematics of the vehicle stored in the flash memory of the socket -Socket 10 founds that the signal 51 goes to output pin 01 and activates it -Finally the trunk light switches on.

Transceiver device according to Fig. 5 The contents and/or tasks of the transceiver blocks A-L are as follows: A Transmit line driver contains a complementary slew rate limited push pull type line driver B Pulse width modulator converts binary quartets to delayed transitions C Bus arbitration detector stops the transmitter when the bus arbitration has lost D Transmit control logic contains a state machine which controls all transmit logic units E IDLE delay detector detects long delays needed for the heart beat genera- tion F Short edge filter utilizes 2 us delay line to remove signal noise

G Sync signal detector restarts both transmit and receive logic when new sync is detected H CRC control logic is used for error detection calculations during transmit and receive I Receive line driver contains a differential low pass filterering amplifier and a Schmitt trigger J Long edge filter utilizes 4 uS delay line to remove signal noise K Pulse width demodulator converts delayed transitions back to binary quar- tets L Receive control logic contains a state machine which controls all receive logic units.