Title:
METHOD AND SYSTEM FOR GENERATING CIRCUIT INFORMATION FOR PROGRAMMABLE LOGIC DEVICE, CIRCUIT TESTING DEVICE AND COMPUTER PROGRAM THEREFOR, DEVICE AND COMPUTER PROGRAM FOR CREATING CIRCUIT DATA, AND COMPUTER READABLE STORAGE MEDIUM
Document Type and Number:
WIPO Patent Application WO/2012/070669
Kind Code:
A1
Abstract:
Provided is a system for testing a programmable logic device (PLD) and generating circuit information by which the utilization rate of a partially defective PLD can be improved and the utilization rate can be quantitatively understood. This system for testing and generating circuit information comprises a testing means for testing a failed PLD that has failed a test of PLD programmable resources, and generating information that specifies the defective programmable resources by testing the malfunctioning programmable resources inside the defective PLD, and a generating means for generating circuit information that will avoid the defective malfunctioning programmable resources and, using the PLD, realize the desired logic circuit on the basis of information that represents the desired logic circuit and the information that has been generated by the testing means and that specifies the defective programmable resources.
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Inventors:
AWASHIMA TORU (JP)
Application Number:
PCT/JP2011/077284
Publication Date:
May 31, 2012
Filing Date:
November 21, 2011
Export Citation:
Assignee:
NEC CORP (JP)
AWASHIMA TORU (JP)
AWASHIMA TORU (JP)
International Classes:
H03K19/177
Domestic Patent References:
| WO2000062339A1 | 2000-10-19 |
Foreign References:
| JP2001136058A | 2001-05-18 | |||
| JP2005328462A | 2005-11-24 |
Attorney, Agent or Firm:
SHIMOSAKA, NAOKI (JP)
Naoki Shimosaka (JP)
Naoki Shimosaka (JP)
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Claims: