COMBINATION INTEGRATED CIRCUIT

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and benefits of Chinese Patent Application Serial No.

201210364697.1, filed with the State Intellectual Property Office of P. R. China on September 26, 2012, the entire content of which is incorporated herein by reference.

FIELD

Embodiments of the present disclosure generally relate to a technical field of testing a digital integrated circuit, and more particularly to a method for testing a broadside path delay fault of a digital combination integrated circuit.

BACKGROUND

Faults such as a single stuck-out fault, a transition fault and a delay fault generally occur in a digital integrated circuit test. With the development of high integration and low power consumption of the integrated circuit chip, the delay fault becomes much easier to occur in the integrated circuit chip applications. The path delay fault is an important part of the delay fault, which focuses on an influence of a delay accumulation caused by connecting wires between gates on a delay time of a whole path. With an increment of the size of the integrated circuit chip, the path delay fault increases exponentially, thus increasing the test difficulty.

Aiming at decreasing the time of testing the path delay fault, Pomeranz and Reddy has already provided a selection method based on the key path, which compresses test vectors of one test path or a plurality of test paths having a maximum number of gates, without caring about the testability of the test paths. For the large size of integrated circuit, the above selection method will generate a lot of redundant test paths.

SUMMARY

Embodiments of the present disclosure seek to solve at least one of the problems.

One objective of the present disclosure is to provide a method for testing a broadside path delay fault of a digital combination integrated circuit which has a short test time and high test efficiency.

According to embodiments of the present disclosure, a method for testing a broadside path delay fault of a digital combination integrated circuit is provided. The method comprises steps of: determining a testable path circuit from the digital combinational integrated circuit, in which the testable path circuit comprises a first plurality of test paths, and each test path has a plurality of fan-outs; ranking the first plurality of test paths in accordance with a number of fan-outs from large to small, and selecting a predetermined number of test paths ranked high to generate a test path set; obtaining at least one first test path from the test path set, calculating an influence cone and a test vector of the at least one first test path, and deleting the at least one first test path from the test path set, in which the first test path is the test path having a maximum number of fan-outs; selecting a labeled path from the at least one first test path, in which the labeled path is the first test path having a minimum overlap ratio with the influence cone; determining whether the labeled path meets a compression requirement; if yes, compressing the labeled path to obtain a test pair of the labeled path and updating the test vector of the labeled path according to the test pair to obtain a final test vector of the labeled path; repeating above steps until there is no test path in the test path set to obtain a final test vector set; and performing a fault simulation according to the final test vector set on the testable path circuit to detect a fault path, and deleting the fault path from the testable path circuit and the test path set.

In one embodiment of the present disclosure, determining a testable path circuit from the digital combinational integrated circuit comprises: determining whether any fan-out point of the one test path is in a first testable path sub-circuit, wherein the first testable path sub-circuit comprises a second plurality of test paths having a same input; if no, determining a second testable path sub-circuit according to the one test path, and if yes, determining whether the one test path is overlapped with a fan-out branch of the first testable path sub-circuit; if yes, determining whether each gate in the one test path is the same as a corresponding gate of the first testable path sub-circuit; and if yes, using input points of the each gate in the one test path as an input branch of the corresponding gate of the first testable path sub-circuit.

According to embodiments of the present disclosure, a computer program comprising computer instructions for executing the above method and a computer readable storage medium comprising a computer program for executing the above method are disclosed.

With the method for testing the broadside path delay fault of the digital combination integrated circuit, redundant process during the fault simulation is eliminated, a linked list for recording fault chains is not required, problems of the fault simulation caused by large data is overcome, and the memory requirement of the program is reduced greatly, without losing a fault coverage. Furthermore, with the method of establishing the testable path circuit according to an embodiment of the present disclosure, the time of establishing the testable path circuit is decreased. According to the present disclosure, the number of path delay test vectors is decreased, the test time of the integrated circuit chip is reduced, and the test efficiency is enhanced.

Additional aspects and advantages of embodiments of present disclosure will be given in part in the following descriptions, become apparent in part from the following descriptions, or be learned from the practice of the embodiments of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects and advantages of embodiments of the present disclosure will become apparent and more readily appreciated from the following descriptions made with reference to the accompanying drawings, in which:

Fig. 1 is a flow chart of a method for testing a broadside path delay fault of a digital combination integrated circuit according to an embodiment of the present disclosure;

Fig. 2a is a schematic diagram of a threshold logic conflict during a compression in a robust circuit according to an embodiment of the present disclosure;

Fig. 2b is a schematic diagram of a threshold logic conflict during a compression in a robust circuit according to another embodiment of the present disclosure; and

Fig. 3 is a schematic diagram of a fault simulation according to an embodiment of the present disclosure. DETAILED DESCRIPTION

Reference will be made in detail to embodiments of the present disclosure. The embodiments described herein with reference to drawings are explanatory, illustrative, and used to generally understand the present disclosure. The embodiments shall not be construed to limit the present disclosure. The same or similar elements and the elements having same or similar functions are denoted by like reference numerals throughout the descriptions.

Moreover, terms of "first" and "second" are only used for description and cannot be seen as indicating or implying relative importance.

In the following, the method for testing the broadside path delay fault of the digital combination integrated circuit according to embodiments of the present disclosure will be described in detail with reference to drawings.

Fig. 1 is a flow chart of a method for testing a broadside path delay fault of a digital combination integrated circuit according to an embodiment of the present disclosure. As shown in Fig. 1, the method comprises the following steps.

At step 101, a testable path circuit is determined from the digital combination integrated circuit, in which the testable path circuit comprises a first plurality of test paths (i.e., all the test paths of the digital combination integrated circuit), and each test path has a plurality of fan-outs.

In one embodiment, the digital combination integrated circuit comprises a first type of circuit and a second type of circuit. For example, the first type of circuit may be a non-robust circuit, and the second type of circuit may be a robust circuit.

Specifically, the testable path circuit is determined from the digital combination integrated circuit as follows. Firstly, one test path is selected from the first plurality of test paths, and then it is determined whether each fan-out point of the one test path is in a first testable path sub-circuit (i.e., the current testable path sub-circuit), in which the first testable path sub-circuit comprises a second plurality of test paths having a same input. When neither fan-out point of the one test path is in the first testable path sub-circuit, a second testable path sub-circuit (i.e., a new testable path sub-circuit) is determined according to the one test path. When all the fan-out points of the one test path are in the first testable path sub-circuit, it is further determined whether the one test path is overlapped with a fan-out branch of the first testable path sub-circuit. When the one test path is overlapped with a fan-out branch of the first testable path sub-circuit, it is determined whether each gate in the one test path is the same as a corresponding gate of the first testable path sub-circuit. When each gate in the one test path is the same as a corresponding gate of the first testable path sub-circuit, input points of the each gate in the one test path is used as an input branch of the corresponding gate of the first testable path sub-circuit. Thus, the one test path is added into the testable path circuit, and then the one test path is deleted from the first plurality of test paths. The above steps are repeated until all the first plurality of test paths are added into the testable path circuit.

At step 102, the first plurality of test paths are ranked in accordance with a number of fan-outs from large to small, and a predetermined number of test paths ranked high are selected to generate a test path set.

In embodiments of the present disclosure, the predetermined number may be set according to actual requirements. In theory, the larger the predetermined number is, the higher the compression ratio is; and the smaller the predetermined number is, the lower the compression ratio is. In one embodiment of the present disclosure, the predetermined number of test paths may have the same number of fan-outs, or may have different numbers of fan-outs which are ranked from large to small.

In another embodiment of the present disclosure, after the predetermined number of test paths are selected, they are deleted from the testable path circuit.

At step 103, at least one first test path is obtained from the test path set, an influence cone and a test vector of the at least one first test path are calculated, and the at least one first test path is deleted from the test path set, in which the first test path is the test path having a maximum number of fan-outs.

From the above, it can be seen that there may be one first test path or a plurality of first test paths having the same number of fan-outs.

In one embodiment of the present disclosure, the influence cone comprises a first type of influence cone corresponding to the first type of circuit and a second type of influence cone corresponding to the second type of circuit.

Further, the first type of influence cone may correspond to the non-robust circuit, and may be represented as { A} U IN(G1), in which A is a source of the broadside path delay fault, and Gl are sinks of the broadside path delay fault in a second frame of the testable path circuit. The second type of influence cone may correspond to the robust circuit, and may be represented as IN(G) U IN(G1), in which G are sinks of the broadside path delay faults in a first frame of the testable path circuit. In one embodiment, corresponding to the non-robust circuit and robust circuit, the path delay fault comprises a non-robust path delay fault and a robust path delay fault. The robust path delay fault refers to the path delay fault which still can be tested even when there are other delay faults in the circuit. When the signal logic value on the transfer path of the second frame circuit changes from a controlling value to a non-controlling value, the signal logic values on all the non-fault paths of the second frame circuit are assigned non-controlling values. When the signal logic value on the transfer path of the second frame circuit changes from a non-controlling value to a controlling value, the signal logic values on all the non-fault paths of the second frame circuit are assigned controlling values, and the signal logic values on the non-fault paths of the first frame circuit should be set to be X (an uncertain value). The non-robust path delay fault refers to the path delay fault which can be tested when there is no other delay fault (i.e., the signal logic values on the non-fault paths of the two frame circuits are not non-controlling value).

At step 104, a labeled path is selected from the at least one first test path, in which the labeled path is the first test path having a minimum overlap ratio with the influence cone. In other words, when there is only one test path having a maximum number of fan-outs in the test path set, the only one test path is selected to be the labeled path. When there are a plurality of test paths having the maximum number of fan-outs in the test path set, the first test path having the minimum overlap ratio with the influence cone is selected to be the labeled path.

At step 105, it is determined whether the labeled path meets a compression requirement. In one embodiment of the present disclosure, it is determined whether a sensitization requirement of the labeled path is in conflict with a current logic gate value, if yes, the labeled path cannot be compressed, and if no, the labeled path can be compressed. For example, it is determined whether an intersection set between the test vector and the influence cone of the labeled path is empty, if yes, the labeled path meets the compression requirement, and if no, it is determined whether the labeled paths meets the compression requirement according to other technologies which are well known for those skilled in the art, and the detailed description thereof will be omitted here.

Specifically, for the robust circuit, two influence cones of two test paths are calculated, in which one influence cone is IN(G) U IN(G1) and the other influence cone is IN(G') U IN(Gl'), and then it is determined whether the intersection set between the two influence cones (i.e., (IN(G) U IN(G1)) Π (IN(G') U IN(G1'))) is empty or the overlap parts of the two influence cones have the same value, if yes, the two test paths can be compressed, and if no, the two test paths cannot be compressed.

For the non-robust circuit, two influence cones of two test paths are calculated, in which one influence cone is {A) U IN(Gl) and the other influence cone is {A' } U IN(Gl'), and then it is determined whether the intersection set between the two influence cones (i.e., ({A} U IN(G1)) Π ({ A' } U IN(G1'))) is empty or the overlap parts of the two influence cones have the same value, if yes, the two test paths can be compressed, and if no, the two test paths cannot be compressed. Fig. 2a is a schematic diagram of a threshold logic conflict during a compression in a robust circuit according to an embodiment of the present disclosure. As shown in Fig.2a, in order to transfer the path delay default P2 to the output, the logic values of the ends A, A', B and B' should be assigned 1, 0, 1, 0 respectively. In the first frame circuit, the sensitization values to the ends A and B are in conflict with the logic values required by the transfer paths PI and P3, and thus the compression fails. Fig. 2b is a schematic diagram of a threshold logic conflict during a compression in a robust circuit according to another embodiment of the present disclosure. As shown in Fig. 2b, in order to transfer the path delay fault P2 to the output, the logic values of the ends C and C should be assigned 0, and in order to transfer the path delay fault PI, the logic values of the ends A and A' should be assigned 1. If the logic values of the ends A and A' meet the requirement, the logic values of the ends C and C must be assigned other values rather than 0, and thus a conflict is generated and the compression fails.

At step 106, the labeled path is compressed to generate a test pair of the labeled path and then the test vector of the labeled path is updated according to the test pair to obtain a final test vector of the labeled path. The test pair is also a test vector. Specifically, the final test vector of the labeled path is a union set of the test vector and the test pair of the labeled path.

At step 107, it is determined whether there is no test path in the test path set, if no, return to step 103, and if yes, a final test vector set is obtained and then execute step 108. In other words, the above steps 103 to 106 are repeated until there is no test path in the test path set to obtain the final test vector set.

At step 108, a fault simulation is performed according to the final test vector set on the testable path circuit to detect a fault path, and then the fault path is deleted from the testable path circuit and the test path set.

Specifically, the final test vector is firstly input into the testable path circuit to perform a three-valued logic simulation, and then one input of a gate at an output of the testable path circuit is selected as a test input. When the tested integrated circuit is the non-robust circuit, it is checked whether other inputs in the second frame of the testable path circuit are assigned non-controlling values. When the tested integrated circuit is the robust circuit, it is checked whether other inputs in the first frame of the testable path circuit are assigned non-controlling values and a transition from the non-controlling value to a controlling value occurs at a current tested path. If the above conditions are met, the test input is backtracked until a primary input or a pseudo -primary input of the testable path circuit is reached. When it is successful to backtrack to the primary input or the pseudo-primary input, the corresponding path is tested to be the fault path.

In another embodiment, when each fan-out branch with the primary input or the pseudo-primary input as a source has been detected, the primary input or the pseudo-primary input and the fan-out branches corresponding to the primary input or the pseudo-primary input may be deleted from the testable path circuit.

Fig.3 is a schematic diagram of a fault simulation according to an embodiment of the present disclosure. As shown in Fig. 3, the test vectors of the two frame circuits are (1, 0, 0, 1) and (1, 1, 1, 1) respectively. The test vectors are input into the testable path circuit to perform the three- valued logic simulation. Assuming that the output port 14 is selected to perform a backtracking selection and the port 11 is selected as a test input port, then it is checked whether the non-transmission port 12 is assigned a non-controlling value with respect to the test input port, if yes, it is checked whether the logic value of the non-transmission port 2 to the port 8 having a transition along the falling edge is 1, if yes, go on backtracking and transmit to the port 3. When it is successfully transmitted to the primary input 3, the path 3-8-11-14 is tested. Similarly, the paths 3-7-10-13, 3-9-12-14, 4-9-12-14, 4-7-10-13, and 4-8-11-14 can be tested. These paths are deleted after being tested. Further, it is checked whether each path with the primary input or the pseudo-primary input as the source is deleted, and if yes, the corresponding primary input or the pseudo-primary input is deleted.

In the following, the path selection efficiency of the method according to the present disclosure will be experimentally verified by taking a Dell precPsPon 690 work station as an experiment platform. Table 1 shows experiment results by applying the method of the present disclosure to a PSCA circuit, and Table 2 shows experiment results by applying the conventional method to the PSCA circuit, in which "k" represents the number of test paths having the maximum number of fan-outs, "FFs" represents the number of triggers in the circuit, the first "vec" represents the number of test vectors before being compressed, "paths" represents the number of test paths, the second "vec" and the third "vec" represents the number of test vectors after being compressed, "comp" represents the ratio between the number of test vectors and that of fault paths, "select" represents the path selection time, and "CPU" represents the consuming time for generating the test vectors. It can be seen from Table 1 and 2 that the number of test paths increases with the increment of k, however, the increment amount of the number of test paths is less than that of k. Furthermore, it is obvious that with the method according to the present disclosure, the number of test vectors is decreased efficiently, and the time for generating the test vectors is shortened.

Table 1 experiment results of the method according to the present disclosure

Table 2 experiment results of the conventional method

With the method for testing the broadside path delay fault of the digital combination integrated circuit, redundant process during the fault simulation is eliminated, a linked list for recording fault chains is not required, problems of the fault simulation caused by large data is overcome, and the memory requirement of the program is reduced greatly, without losing a fault coverage. Furthermore, with the method of establishing the testable path circuit according to an embodiment of the present disclosure, the time of establishing the testable path circuit is decreased. According to the present disclosure, the number of path delay test vectors is decreased, the test time of the integrated circuit chip is reduced, and the test efficiency is enhanced.

In the flow chart or any process or method description described with other manner may be construed to means including one or more modulate, segment and parts of the available code of the procedure of the process or for realizing a certain logical function, and the scope of the actualizing scheme selected preferentially of the present disclosure includes other actualization, and the function may be implemented with the basic coinstantaneous method or the contrary order, according to the related function, and the function may be not implemented as the order showed or discussed, which is understood by those skilled of the technical field of the embodiments of the present disclosure.

The logic and/or procedure described with other manner or showed in the flow chart, for example, may be considered to be the sequencer list for executing the instruction for realizing the logical function, concretely actualized in the readable medium in any computer to be used by the instruction execution system, device and equipment (such as the system based on the computer, the system including a processor and other system for fetching the instruction and executing the instruction from the instruction execution system, device and equipment ), or used with the instruction execution system, device and equipment. As to the specification, "the readable medium in any computer" may be any device, and the device may include, store, communicate, diffuse or transmit procedure to be used by the instruction execution system, device and equipment or the device is used with the instruction execution system, device and equipment. The more concrete demonstration of the readable medium in any computer (the limited list) comprises: an electronic connection (an electronic device) with one or more wires, a portable computer box (a magnetism device), a random-access memory (RAM), a read-only memory (ROM), a erasable-programmable read-only memory (EPROM or flash memory), a optical fiber device and a portable compact disk read-only memory (CDROM). In addition, the readable medium of computer is even a paper or other appropriate medium to print the procedure on it, because the procedure obtained with electronic form may be edited, decrypted or dealt with other appropriate manner by optical scanning the paper or other medium, and then the procedure worked will be stored in the computer memory.

It is understood that each part of the present disclosure may be actualized by the hardware, software, firmware or their assembly. In the actualization manner, a plurality of procedure or manner may be actualized by the software or firmware, and the software or the firmware are stored in the memory and executed by the appropriate instruction execution system. For example, if the procedure or manner is actualized by the hardware, as the same as another actualization manner, the procedure or manner may be actualized by one of the following techniques of the field known to all or their assembly: a discrete logic circuit of the logic gate circuit for actualizing logic function to data signal, a special integrate circuit having an appropriate combination logic gate circuit, programmable gate array (PGA), field programmable gate array (FPGA) and so on.

All or parts of the procedure schlepped in the method for actualizing the embodiments of the present disclosure are understood by those common skilled of the technical field, which is achieved by the hardware dictated by the procedure. The procedure may be stored in a computer readable storage medium, and the procedure includes one of the procedures of the embodiments of the present disclosure or their assembly when it is actualized.

In addition, each function cell of the embodiments of the present disclosure may be integrated into a processing module, and these cells may physically exist respectively, and also two or plural of the cells are integrated into a processing module. The integrated module is not only actualized with the hardware, but also actualized with the software function module. When the integrated module is actualized with the software function module to be sold or used as an unattached production, the integrated module may be stored in a computer readable storage medium.

The storage medium mentioned above may be read-only memory, disk or CD.

Reference throughout this specification to "an embodiment," "some embodiments," "an example," "a specific example," or "some examples," means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. The appearances of the phrases throughout this specification are not necessarily referring to the same embodiment or example of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

Although explanatory embodiments have been shown and described, it would be appreciated by those skilled in the art that the above embodiments cannot be construed to limit the present disclosure, and changes, alternatives, and modifications can be made in the embodiments without departing from spirit, principles and scope of the present disclosure.