METHOD FOR TESTING INTEGRATED CIRCUITS - KONINKL PHILIPS ELECTRONICS NV

Title:

METHOD FOR TESTING INTEGRATED CIRCUITS

Document Type and Number:

WIPO Patent Application WO2002037130

Kind Code:

A3

Abstract:

The method according to the present invention relates to the detection of fabrication defects in static CMOS circuits. An integrated circuit, for instance, having a gate (12, 13) additionally includes two sleep transistors (14, 15) and two pull transistors (16, 17) of regular threshold and low leakage. The sleep transistors are used to break up the gate into two parts (12; 13) for allowing a pair of response sequences. The two responses are either checked for consitency or compared against a predetermined expected response sequence. The usage of the pull transistors is as passive loads such as to enable pseudo NMOS and pseudo PMOS operation. One of the advantages of the method according to the invention, is that it is insensitive to MOSFET leakage currents.

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Inventors:

FELBER NORBERT
KAESLIN HUBERT

Application Number:

PCT/EP2001/012400

Publication Date:

March 27, 2003

Filing Date:

October 23, 2001

Export Citation:

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Assignee:

KONINKL PHILIPS ELECTRONICS NV (NL)

International Classes:

G01R31/317; G01R31/28; G11C29/00; H01L21/822; H01L27/04; (IPC1-7): G11C29/00

Foreign References:

EP0953989A2

1999-11-03

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