NETWORKS RELATED APPLICATIONS

This patent claims the priority to and the benefit of U.S. Provisional Patent Application Serial No. 62/502,388, filed May 5, 2017, which is hereby incorporated by reference in its entirety. FIELD OF THE DISCLOSURE

This disclosure relates generally to networking, and, more particularly, to methods and apparatus for time sensitive network communication in wireless networks. BACKGROUND

Time Sensitive Networks (TSN) are networks that provide time synchronization and timeliness (deterministic latency and

reliability/redundancy) guarantees to, for example, critical data streams.

Industrial control and smart factories are common applications for TSN.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an example time sensitive network capable wireless network environment.

FIG. 2 is a schematic illustration of an example transmission cycle schedule of the environment of FIG. 1.

FIG. 3 is flowchart illustrating example instructions that may be executed to implement time sensitive networking in a wireless device.

FIG. 4 is a schematic illustration of an example beacon transmission timing.

FIG. 5 is a schematic illustration of an example beacon transmission and receiving timing. FIG. 6 is a block diagram of another example time sensitive network capable wireless network environment.

FIG. 7 is a schematic illustration of an example communication schedule of the environment of FIG. 6.

FIG. 8 is a block diagram of another example time sensitive network capable wireless network environment.

FIG. 9 is a schematic illustration of an example communication schedule of the environment of FIG. 8.

FIG. 10 is a block diagram of a radio architecture in accordance with some embodiments;

FIG. 11 illustrates a front-end module circuitry for use in the radio architecture of FIG. 10 in accordance with some embodiments;

FIG. 12 illustrates a radio IC circuitry for use in the radio architecture of FIG. 10 in accordance with some embodiments;

FIG. 13 illustrates a baseband processing circuitry for use in the radio architecture of FIG.10 in accordance with some embodiments.

FIG. 14 is a block diagram of an example processing device that may execute the instructions of FIG. 3 to implement a time sensitive network capable wireless device.

DETAILED DESCRIPTION

Wireless communication enables rapid and low-cost deployment of communication networks. In addition, wireless communication enables the connectivity of devices that are portable, distant, or otherwise unable to be connected via wired networks. However, to enable wireless networking to be utilized in time sensitive applications (e.g., smart factories), it is desirable to provide Wireless TSN. Wireless TSN may be beneficial in the Industrial Internet of Things (IOT) market as well as other fields. Wireless connectivity in a control loop can enable new applications such as autonomous guided vehicles and robot swarms, as well as provide great benefits through wiring replacement including easy re-configurability, cost-reduction (expensive wiring replacement) and better user experience through un-tethered operation. Time synchronized operation is a common characteristic of TSN applications. TSN Stations (STA) are synchronized to a master reference time and I/O and data processing operations are executed in a deterministic cyclic pattern.

However, there are challenges to applying TSN to wireless networks.

FIG. 1 is a block diagram of an example environment 100 in which an example Programable Logic Controller (PLC) 102 controls the wireless communication of a first wireless device 104 and a second wireless device 106. According to the illustrated example, the environment 100 is an industrial control system environment 100 in which all operations are aligned with a control cycle set by the Programable Logic Controller (PLC) 102 (e.g., an access point (AP), a central controller, etc.). An example control cycle 200 is illustrated in FIG. 2.

As illustrated in FIG. 2, I/O input generated by the example sensor STA 104 is transmitted in a first cycle (cycle 1/iteration 1), processed by the PLC 102 in cycle 2/iteration 2, and an output is generated and transmitted during cycle 3/iteration 3 to a receiving STA 106 (e.g., a receiving STA 106 connected to a motor or other industrial machine). Enabling deterministic transmission of data as well as execution of other device tasks (e.g. network management) within a control cycle facilitates deterministic behavior expected by TSN applications. While the specific cycle times vary depending on the application, supporting operation at 1 msec cycles is expected to enable a wide range of industrial use cases.

While Wi-Fi's gigabit per second (Gbps) data rates (e.g. in Institute of Electrical and Electronic Engineers (IEEE) 802.1 lac, ax and ad/ay) can enable ultra-low latency (e.g., to communicatively couple the devices illustrated in FIG. 1), the non-deterministic nature of the IEEE 802.11 media access control (MAC) and operation in unlicensed spectra imposes new challenges, especially to guarantee reliabilities comparable to wired protocols (e.g.

Ethernet TSN). Furthermore, while Wi-Fi/IEEE 802.11 networks can enable exchange of time synchronization messages (e.g. based on the 802. IAS time synchronization standard) to achieve time synchronized computing required by TSN applications, the actual radio layer operation is not time synchronized. Instead, IEEE 802.11 radios operate on the basis of a random access mode (e.g., CSMA/CA) that can be problematic for cycle-based TSN data communication and processing:

IEEE 802.11 data, control and management frame transmissions are not time synchronized and there are no mechanisms to deterministically align all transmissions with a given control cycle time for the network. In other words, although STA may acquire a single reference time (e.g. through 802. IAS synchronization), the IEEE 802.11 radio operations are not necessarily aligned to such reference time and to a given cycle time;

The IEEE 802.11 CSMA/CA MAC introduces randomness to data and management frame (e.g. beacon) transmissions. For instance, although an Access Point has a Target Beacon Transmission Time (TBTT), the transmission of a beacon may have to be deferred if the medium is busy at the next TBTT. The beacon transmission time is not deterministic and this can cause conflicts for a STA that has to transmit/receive time-critical TSN data streams.

Contention-free access options available in certain IEEE 802.11 modes, such as Service Periods (SPs) in IEEE 802.1 lad, do not have provisions to ensure the SPs are time synchronized across all STA and aligned with the control cycle. Furthermore, previous solutions to support TSN applications based on contention-free access through reserved SPs and dedicated channels do not address the problem of aligning the IEEE 802.11 operation to a deterministic control cycle across the network.

Methods and apparatus disclosed herein implement time sensitive network applications in wireless networks (e.g., IEEE 802.11 Wi-Fi networks). As used herein, a Wi-Fi network refers to a network in which devices (e.g., wireless devices, access points, central controllers, etc.) wirelessly communicate according to one of the protocols defined in IEEE 802.11. The methods and apparatus disclosed herein may be utilized with other types of wireless communications (e.g., wireless communication protocols other than Wi-Fi) as well. Wireless communication may be utilized in addition to or as an alternative to wired communication. The Wi-Fi network may include devices that communicate in a channel(s) of the 2.4 GHz spectrum, in a channel(s) of the 5 GHz spectrum, in a channel(s) of the 60 GHz spectrum, etc. In some examples disclosed herein, firmware, drivers, software, etc. of a wireless device utilizing Wi-Fi may be upgraded, updated, replaced, etc. with firmware, drivers, software, etc. that support time sensitive networks according to the methods and apparatus disclosed herein.

In some examples disclosed herein, an AP or other network element coordinates communication among STAs to implement a TSN capable Wi-Fi network in which communications are deterministically scheduled within control cycles. In some examples disclosed herein, wireless stations are synchronized with an AP that controls transmissions to ensure that

communications are aligned with cycle times set by the AP and to ensure that the communications do not interrupt other communications (e.g., network beacons transmitted by the AP).

Some examples disclosed herein operate in an environment in which a

TSN capable Wi-Fi network can be managed and there are no unmanaged nearby Wi-Fi STA/networks. This is a reasonable operating assumption for most industrial and enterprise environments where the TSN application, for example, could be used. In some examples disclosed herein, a STA with critical TSN data streams will request access with specified QoS requirements (e.g. defined in a traffic specification (TSPEC)) that characterizes the TSN requirements. Thus, the AP of the TSN capable Wi-Fi network would, therefore, be aware of TSN traffic streams and can schedule TSN data stream transmissions for all TSN STAs in accordance with the methods and apparatus disclosed herein. Alternatively, any other approach for alerting the AP to the TSN preference/requirement of an STA may be utilized. In some examples disclosed herein, APs and STAs within the TSN capable Wi-Fi network synchronize their clock to a master reference time as defined in, for example, the IEEE 802. IAS standard.

In some examples disclosed herein, to A) enable STAs to periodically receive management frames (e.g. beacons) to maintain association and TSN configuration information (e.g. dedicate TSN Channels) and/or B) enable STAs to receive beacons after establishing TSN streams, beacon transmissions are aligned with the beginning of a cycle time. In some such examples, the beacon period is defined as a function of the cycle time. For example, the Target Beacon Transmission Time (TBTT) may be defined as TBTT = N x Cycle-Time, where the Cycle-Time is defined based on, for example, the IEEE 802.11 Time Unit (TU). In some examples, the Cycle-Time is equal to the TU and N=100, which would result in TBTT = 102.4 ms, which is a typical TBTT value used in practice.

In some examples, APs and STAs in the TSN capable Wi-Fi network track the Absolute Cycle Number (ACN), which is the total number of cycles that have elapsed since the start of the network and/or an arbitrary time determined by the AP (the ACN may also be globally set by a TSN network management entity). The ACN increments globally across the network every Cycle-Time. In some examples, the Cycle-Time and ACN are advertised in beacon frames and TSN capable STAs decode a beacon frame and update its Cycle-Time and ACN before trying to access the channel.

FIG. 3 is a block diagram of an example environment 300 in which wireless stations (STA) 302 communicate with an access point (AP) 304. While two STAs 302 and AP 304 are included in the example environment 300, any number of STAs and APs may be utilized in an environment.

The STAs 302 of the illustrated example are wireless devices that have a need for time sensitive networking. For example, the STAs 104, 106 may be implemented by the STAs 302. Alternatively, the STAs 302 may be any type of wireless device (e.g., a user device, a server device, an embedded computing device, a portable computing device, a manufacturing device, a sensor, a device controller, computing device installed in a vehicle, etc.). The example STAs 302 operate according to a protocol established under IEEE 802.11. For example, the STAs 302 may operate under an existing IEEE 802.11 protocol that has been modified to include the TSN functionality in accordance with the methods and apparatus disclosed herein.

The example STAs 302 include example TSN controllers 306 to enable the STAs 302 to conduct time sensitive communications. According to the illustrated example, the TSN controllers 306 coordinate the communications of example STAs 302 according to a cycle schedule defined by the example AP 304. The operation of TSN controllers 306 is described in further detail in conjunction with FIG. 4.

The AP 304 of the illustrated example is a standalone wireless communication device that directs/controls communication within a communication network including the STAs 302. The AP 304 may alternatively be integrated into one of the STAs 302, may be integrated into any other device, may include other functionalities (e.g., may including network switching functionality, network routing functionality, network bridging functionality, etc.). While environment 300 includes a single AP 304, an environment may include any number of APs.

The AP 304 of the illustrated example, is configured to receive requests from the STAs 302 to enable time sensitive networking. For example, the AP 304 may receive a request identifying quality of service (QoS) requirements (e.g., defined in a traffic specification (TSPEC)) of the STAs 302. In response to such a request, the AP 304 schedules TSN data stream transmission for all TSN capable STAs 302. For example, the AP 304 may synchronize the clocks of all devices to a master reference time (e.g., according to IEEE 802. IAS). In addition, the AP 304 transmits beacons to transfer communication cycle parameters to the STAs 302. The example AP 304 tracks an absolute cycle number (ACN) and transmits the ACN in the and a duration of a cycle (i.e., a Cycle-Time) in the beacon. The AP 304 may additional transmit a target beacon transmission time (TBTT) in the beacon. For example, the Target Beacon Transmission Time (TBTT) may be defined as TBTT = N x Cycle-Time, where the Cycle-Time is defined based on, for example, the IEEE 802.11 Time Unit (TU).

In operation of environment 300, AP 304 periodically transmits beacons with TSN network information (e.g., TBTT, Cycle-Time, ACN). STAs 302 scans for beacons when initializing/joining a network. STAs 302 record the TSN network information and align communications according to the network information. For example, STAs 302 adjust communication schedules to align transmissions with the cycle. In addition, the STAs 302 avoid transmitting at a time that will overlap with a beacon transmission (e.g., hold a transmission opportunity (TXOP) that will not end before the next beacon transmission is expected).

FIG 4 is a block diagram of an example implementation of the TSN controller 306 of FIG. 3. The example TSN controller 306 of FIG. 3 includes an example beacon receiver 402, an example parameter extractor 404, an example cycle handler 406, and an example transmission controller 408.

The example beacon receiver 402 receives beacons transmitted within the example environment 300 (e.g., beacons transmitted by the example AP 304. For example, beacon receiver 402 may be wireless transceiver and/or may be coupled with a wireless transceiver. According to the illustrated example, the beacon receiver 402 does not transmit a probe for beacons within the TSN environment 300. In some examples, the beacon receiver 402 does not transmit a request for any type of frames before receiving a beacon and detecting the cycles (e.g., the beacon receiver 402 may only perform passive scanning). Instead, the beacon receiver 402 awaits a beacon that is transmitted on an operating channel. The example beacon receiver 402 transfers the received beacons to the example parameter extractor 404.

The example beacon extractor 404 extracts parameters contained within the beacon. According to the illustrated example, the parameters provide direction from the example AP 304 to instruct the STA 302 how to communicate within the environment 300 to support time sensitive applications. The example beacon extractor 404 extracts a TBTT, a Cycle- Time, and an ACN. The example beacon extractor 404 transfers the extracted parameters to the example cycle handler 406 and the transmission controller 408.

The example cycle handler 406 synchronizes the STA 302 to the Cycle-Time set by the beacon. For example, the cycle handler 406 instructs the transmission controller 408 to align transmissions with the cycles set by the AP 304 and/or to follow a transmission schedule identified in the beacon. Additionally, the example cycle handler 406 determines the next beacon cycle number for the next beacon transmission. For example, according to the illustrated example, the next cycle number is calculated as ACN + TBTT. Alternatively, other approaches for calculating a next cycle number agreed upon by the devices in the example environment 300 may be utilized.

The example transmission controller 408 controls the operation of wireless communication components of the ST A 302 to enforce time sensitive networking. For example, the transmission controller 408 controls the wireless communication components to ensure that a transmission does not overlap with a beacon transmission. For example, the transmission controller 408 determines if a TXOP will overlap with a beacon transmission. If such an overlap will occur, the transmission controller 408 delays and/or shortens the TXOP to the overlap.

While an example manner of implementing the TSN controller 306 of FIG. 3 is illustrated in FIG. 4, one or more of the elements, processes and/or devices illustrated in FIG. 4 may be combined, divided, re-arranged, omitted, eliminated and/or implemented in any other way. Further, the example beacon receiver 402, the example parameter extractor 404, the example cycle handler 406, the transmission controller 408 and/or, more generally, the example TSN controller 306 of FIG. 3 may be implemented by hardware, software, firmware and/or any combination of hardware, software and/or firmware. Thus, for example, any of the example beacon receiver 402, the example parameter extractor 404, the example cycle handler 406, the transmission controller 408 and/or, more generally, the example TSN controller 306 of FIG. 3 could be implemented by one or more analog or digital circuit(s), logic circuits, programmable processor(s), application specific integrated circuit(s)

(ASIC(s)), programmable logic device(s) (PLD(s)) and/or field programmable logic device(s) (FPLD(s)). When reading any of the apparatus or system claims of this patent to cover a purely software and/or firmware

implementation, at least one of the example beacon receiver 402, the example parameter extractor 404, the example cycle handler 406, the transmission controller 408 and/or, more generally, the example TSN controller 306 of FIG. 3 is/are hereby expressly defined to include a non-transitory computer readable storage device or storage disk such as a memory, a digital versatile disk (DVD), a compact disk (CD), a Blu-ray disk, etc. including the software and/or firmware. Further still, the example TSN controller 306 of FIG. 3 may include one or more elements, processes and/or devices in addition to, or instead of, those illustrated in FIG. 4, and/or may include more than one of any or all of the illustrated elements, processes and devices.

A flowchart representative of example machine readable instructions for implementing the TSN controller 306 of FIG. 3 and/or FIG. 4 is shown in FIG. 5. In this example, the machine readable instructions comprise a program for execution by a processor such as the application processor 1210 shown in the example radio architecture 1200 discussed below in connection with FIG. 12 and the processor 1612 shown in the example processor platform 1600 discussed below in connection with FIG. 16. The program may be embodied in software stored on a non-transitory computer readable storage medium such as a CD-ROM, a floppy disk, a hard drive, a digital versatile disk (DVD), a Blu-ray disk, or a memory associated with the processor 1612, but the entire program and/or parts thereof could alternatively be executed by a device other than the processor 1612 and/or embodied in firmware or dedicated hardware. Further, although the example program is described with reference to the flowchart illustrated in FIG. 5, many other methods of implementing the example TSN controller 306 may alternatively be used. For example, the order of execution of the blocks may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks may be implemented by one or more hardware circuits (e.g., discrete and/or integrated analog and/or digital circuitry, a Field Programmable Gate Array (FPGA), an Application Specific Integrated circuit (ASIC), a comparator, an operational -amplifier (op-amp), a logic circuit, etc.) structured to perform the corresponding operation without executing software or firmware.

As mentioned above, the example processes of FIG. 5 may be implemented using coded instructions (e.g., computer and/or machine readable instructions) stored on a non-transitory computer and/or machine readable medium such as a hard disk drive, a flash memory, a read-only memory, a compact disk, a digital versatile disk, a cache, a random-access memory and/or any other storage device or storage disk in which information is stored for any duration (e.g., for extended time periods, permanently, for brief instances, for temporarily buffering, and/or for caching of the information). As used herein, the term non-transitory computer readable medium is expressly defined to include any type of computer readable storage device and/or storage disk and to exclude propagating signals and to exclude transmission media.

"Including" and "comprising" (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim lists anything following any form of "include" or "comprise" (e.g., comprises, includes, comprising, including, etc.), it is to be understood that additional elements, terms, etc. may be present without falling outside the scope of the

corresponding claim. As used herein, when the phrase "at least" is used as the transition term in a preamble of a claim, it is open-ended in the same manner as the term "comprising" and "including" are open ended.

The process of FIG. 5 begins when the beacon receiver 402 initializes the TSN controller 306 (block 500). For example, initialization may include syncing a clock of the STA 302 to a clock of the AP 304.

The example beacon receiver 402 scans for beacons (e.g., no probe requests are utilized) (block 502). Once the beacon receiver 402 detects a beacon, the parameter extractor 404 extracts the TBTT (block 504), cycle time (block 506), and ACN (block 508). The cycle handler 406 synchronizes to the cycle time (block 510). For example, the cycle handler 406 may store the cycle time, set a timer to the cycle time, and/or trigger

transmissions/operations aligned with the cycle time (e.g., as discussed in conjunction with FIG. 7).

The cycle handler 406 calculates the next beacon cycle number of the next beacon transmission as ACN + TBTT (block 512). The transmission handler 408 determines if a TXOP will conflict with the next beacon transmission (block 514). When the next TXOP will conflict with the next beacon transmission, the transmission handler 408 performs control of the TXOP (block 516). For example, the transmission handler 408 may delay the TXOP, may stop the TXOP, may shorten the TXOP, etc. After controlling the TXOP (block 516) or after determining that the TXOP will not interfere with the next beacon (block 512), the beacon receiver 402 records the next beacon at the next cycle number (block 518).

In implementations in which the network operates in multiple channels, the cycle time may be synchronized across all channels as illustrated in FIG. 6. In this way, if a TSN STA has an idle cycle, the example STA 302 can perform other tasks in the operating channel. In some examples, the STA 302 may tune to the operating channel to receive a beacon without interfering with the next TSN transmission in a dedicated TSN channel. In some examples, transmissions in the TSN channels are expected to be scheduled by the AP 304, which is aware of the deterministic traffic requirements of each TSN data stream. Moreover, any given TSN STA 302 may not transmit and receive during every cycle. Therefore, the AP 304 can schedule the TSN transmissions in a way to avoid overlapping with beacon transmissions. In some cases, overlapping with certain beacons may still occur without impacting the operation of the TSN STA 302, as the TSN STA 302 may not need to receive every beacon transmission. In some examples, if there is overlapping with all beacons, dedicated management information may be provided to the STA 302 by another transmission type.

In order to ensure beacons are transmitted at the beginning of every Nth cycle (TBTT= N x Cycle-Time), some examples of the cycle handler 406 utilize channel access rules (illustrated by FIG. 7) that include:

1) APs transmit beacons 702 after a cycle transmission offset

(cycleTxOffset) (without contention) within the target beacon cycles. STAs 302 prepare to receive the beacon 704 (by turning on, initiating, and/or enabling their Rx and/ or tuning to the operating channel) a cycle receive offset (cycleRxOffset) after the beginning of the cycle;

2) All STAs 302 defer access to beacon at TBTT (e.g., by setting their network allocation vector (NAV) to indicate the channel is busy at the next TBTT); 3) All TXOPs shall end before the next beacon. Since all STA 302 keep track of the ACN and the next beacon cycle, the STAs can determine whether a TXOP may cross the next beacon cycle and, therefore, either adjust its transmission to end before the next beacon cycle or defer its transmission for after the beacon cycle.

In case the beacon transmission does not occupy the whole cycle, the remainder of the beacon cycle may be used for other frame transmissions. The AP 304 can use priority access, but transactions with TSN STAs 302 should not exceed the cycle boundary (e.g., STAs may configure their maximum TXOP limit according to the duration of the cycle).

In some examples, the AP 304 may transmit downlink TSN data in the remainder of the beacon cycle in order to meet TSN stream requirements. In such examples, the TSN transmission may start short interframe space (SIFS) time after the beacon and it may be allowed to cross the cycle boundary into the first cycle after the beacon.

As used herein, a TSN stream is defined by a constant packet size and packet inter-arrival time, which can be specified in units of cycles. The TSN STA 302 may handle multiple streams, but a typical case is one Uplink (I/O input) and one Downlink (I/O Output) stream. Furthermore, for a given STA 302, I/O input and output do not happen in the same cycle (they are separated by a fixed number of cycles in order to account for processing cycles required at the PLC).

Once AP 304 and STAs 302 are aligned with the cycle-time, the TSN data streams can be scheduled within the appropriate cycles. Therefore, according to the illustrated examples, all TSN transmissions must be contained within a cycle-time. In one embodiment, each cycle defines a Service Period (SP), which can be assigned to a pair of devices (Tx-Rx link) for the entire cycle duration. The schedule for a given TSN stream can be defined by (startingCycleNumber, Period, Repetitions, Action), where:

StartingCycleNumber = first cycle allocated to the TSN stream;

Period= number of cycles between SPs (cycles) allocated to the TSN stream; Repetition = number of SPs that the schedule is valid for. For instance, repetition can be used to schedule a TSN stream with a specific start and end time. If the Repetitions are not defined, the schedule can be valid indefinitely, or until the STA 302 is notified by the AP that the schedule needs to be updated.

Action = indicates the action expected for the STA in this TSN stream, which could be Tx or Rx a frame.

FIG. 8 is a block diagram of an example TSN capable Wi-Fi network 800 in which multiple TSN streams are scheduled within different cycles (as illustrated in FIG. 9) enabling synchronized multi-hop communication from STA 802 A to STA B 804 and STA C 806 under the control of the AP 808. STA A 802 transmits to STA B 804 in cycle 2, STA B 804 processes the data in cycle 3 and transmits to STA C 806 in cycle 4. For example, one or more of the STA 802-806 transmits information about an application (or operation, control system, etc.) to the example AP 808 or any network device (e.g., a controller, central station, primary device, elected device, etc.). The example AP 808 determines a cycle time to be transmitted to the STA 802-806 based on the information about the application (e.g., based on the amount of time that each operation of the application consumes, based on the amount of time that the longest operation of the application consumes, etc.).

FIG. 10 is a block diagram of an example TSN capable Wi-Fi network 1000 including a STA A 1002, STA B 1004, STA C 1006, STA D 1008, and AP 1010. As illustrated in FIG. 11, the example network 1000 may operate across multiple dedicated TSN channels. The same cycle may be assigned to multiple Tx-Rx links if collision-free communication is possible (e.g. multichannels, MU-MTMO) increasing the overall system capacity to support TSN streams. In the network 1000 illustrated in FIG. 10, STA A 1002 and STA B 1004 communicate at the same time as STA C 1006 and STA D 1008, but in different TSN channels.

In case dedicated TSN channels are used, the Non-TSN transmission can happen within the operating channel, as long as they do not

conflict/interfere with TSN data streams. The non-TSN transmissions may cross cycle boundaries in a non-TSN channel, except for the beacon cycle, which must be maintained at deterministic times as described earlier.

FIG. 12 is a block diagram of a radio architecture 1200 in accordance with some embodiments. Radio architecture 1200 may include radio front-end module (FEM) circuitry 1204, radio IC circuitry 1206 and baseband processing circuitry 1208. Radio architecture 1200 as shown includes both Wireless Local Area Network (WLAN) functionality and Bluetooth (BT) functionality although embodiments are not so limited. In this disclosure, "WLAN" and "Wi-Fi" are used interchangeably.

FEM circuitry 1204 may include a WLAN or Wi-Fi FEM circuitry

1204a and a Bluetooth (BT) FEM circuitry 1204b. The WLAN FEM circuitry 1204a may include a receive signal path comprising circuitry configured to operate on WLAN RF signals received from one or more antennas 1201, to amplify the received signals and to provide the amplified versions of the received signals to the WLAN radio IC circuitry 1206a for further processing. The BT FEM circuitry 1204b may include a receive signal path which may include circuitry configured to operate on BT RF signals received from one or more antennas 1201, to amplify the received signals and to provide the amplified versions of the received signals to the BT radio IC circuitry 1206b for further processing. FEM circuitry 1204a may also include a transmit signal path which may include circuitry configured to amplify WLAN signals provided by the radio IC circuitry 1206a for wireless transmission by one or more of the antennas 1201. In addition, FEM circuitry 1204b may also include a transmit signal path which may include circuitry configured to amplify BT signals provided by the radio IC circuitry 1206b for wireless transmission by the one or more antennas. In the embodiment of FIG. 12, although FEM 1204a and FEM 1204b are shown as being distinct from one another, embodiments are not so limited, and include within their scope the use of an FEM (not shown) that includes a transmit path and/or a receive path for both WLAN and BT signals, or the use of one or more FEM circuitries where at least some of the FEM circuitries share transmit and/or receive signal paths for both WLAN and BT signals. Radio IC circuitry 1206 as shown may include WLAN radio IC circuitry 1206a and BT radio IC circuitry 1206b. The WLAN radio IC circuitry 1206a may include a receive signal path which may include circuitry to down-convert WLAN RF signals received from the FEM circuitry 1204a and provide baseband signals to WLAN baseband processing circuitry 1208a. BT radio IC circuitry 1206b may in turn include a receive signal path which may include circuitry to down-convert BT RF signals received from the FEM circuitry 1204b and provide baseband signals to BT baseband processing circuitry 1208b. WLAN radio IC circuitry 1206a may also include a transmit signal path which may include circuitry to up-convert WLAN baseband signals provided by the WLAN baseband processing circuitry 1208a and provide WLAN RF output signals to the FEM circuitry 1204a for subsequent wireless transmission by the one or more antennas 1201. BT radio IC circuitry 1206b may also include a transmit signal path which may include circuitry to up-convert BT baseband signals provided by the BT baseband processing circuitry 1208b and provide BT RF output signals to the FEM circuitry 1204b for subsequent wireless transmission by the one or more antennas 1201. In the embodiment of FIG. 12, although radio IC circuitries 1206a and 1206b are shown as being distinct from one another, embodiments are not so limited, and include within their scope the use of a radio IC circuitry (not shown) that includes a transmit signal path and/or a receive signal path for both WLAN and BT signals, or the use of one or more radio IC circuitries where at least some of the radio IC circuitries share transmit and/or receive signal paths for both WLAN and BT signals.

Baseband processing circuity 1208 may include a WLAN baseband processing circuitry 1208a and a BT baseband processing circuitry 1208b. The WLAN baseband processing circuitry 1208a may include a memory, such as, for example, a set of RAM arrays in a Fast Fourier Transform or Inverse Fast Fourier Transform block (not shown) of the WLAN baseband processing circuitry 1208a. Each of the WLAN baseband circuitry 1208a and the BT baseband circuitry 1208b may further include one or more processors and control logic to process the signals received from the corresponding WLAN or BT receive signal path of the radio IC circuitry 1206, and to also generate corresponding WLAN or BT baseband signals for the transmit signal path of the radio IC circuitry 1206. Each of the baseband processing circuitries 1208a and 1208b may further include physical layer (PHY) and medium access control layer (MAC) circuitry, and may further interface with application processor 1210 for generation and processing of the baseband signals and for controlling operations of the radio IC circuitry 1206.

Referring still to FIG. 12, according to the shown embodiment, WLAN-BT coexistence circuitry 1213 may include logic providing an interface between the WLAN baseband circuitry 1208a and the BT baseband circuitry 1208b to enable use cases requiring WLAN and BT coexistence. In addition, a switch 1203 may be provided between the WLAN FEM circuitry 1204a and the BT FEM circuitry 1204b to allow switching between the WLAN and BT radios according to application needs. In addition, although the antennas 1201 are depicted as being respectively connected to the WLAN FEM circuitry 1204a and the BT FEM circuitry 1204b, embodiments include within their scope the sharing of one or more antennas as between the WLAN and BT FEMs, or the provision of more than one antenna connected to each of FEM 1204a or 1204b.

In some embodiments, the front-end module circuitry 1204, the radio

IC circuitry 1206, and baseband processing circuitry 1208 may be provided on a single radio card, such as wireless radio card 1202. In some other embodiments, the one or more antennas 1201, the FEM circuitry 1204 and the radio IC circuitry 1206 may be provided on a single radio card. In some other embodiments, the radio IC circuitry 1206 and the baseband processing circuitry 1208 may be provided on a single chip or integrated circuit (IC), such as IC 1212.

In some embodiments, the wireless radio card 1202 may include a WLAN radio card and may be configured for Wi-Fi communications, although the scope of the embodiments is not limited in this respect. In some of these embodiments, the radio architecture 1200 may be configured to receive and transmit orthogonal frequency division multiplexed (OFDM) or orthogonal frequency division multiple access (OFDMA) communication signals over a multicarrier communication channel. The OFDM or OFDMA signals may comprise a plurality of orthogonal subcarriers.

In some of these multicarrier embodiments, radio architecture 1200 may be part of a Wi-Fi communication station (STA) such as a wireless access point (AP), a base station or a mobile device including a Wi-Fi device. In some of these embodiments, radio architecture 1200 may be configured to transmit and receive signals in accordance with specific communication standards and/or protocols, such as any of the Institute of Electrical and Electronics Engineers (IEEE) standards including, 802.1 ln-2009, IEEE 802.11-2012, 802.1 ln-2009, 802.1 lac, and/or 802.1 lax standards and/or proposed specifications for WLANs, although the scope of embodiments is not limited in this respect. Radio architecture 1200 may also be suitable to transmit and/or receive communications in accordance with other techniques and standards.

In some embodiments, the radio architecture 1200 may be configured for high-efficiency Wi-Fi (HEW) communications in accordance with the IEEE 802.1 lax standard. In these embodiments, the radio architecture 1200 may be configured to communicate in accordance with an OFDMA technique, although the scope of the embodiments is not limited in this respect.

In some other embodiments, the radio architecture 1200 may be configured to transmit and receive signals transmitted using one or more other modulation techniques such as spread spectrum modulation (e.g., direct sequence code division multiple access (DS-CDMA) and/or frequency hopping code division multiple access (FH-CDMA)), time-division multiplexing (TDM) modulation, and/or frequency-division multiplexing (FDM) modulation, although the scope of the embodiments is not limited in this respect.

In some embodiments, as further shown in FIG. 12, the BT baseband circuitry 1208b may be compliant with a Bluetooth (BT) connectivity standard such as Bluetooth, Bluetooth 13.0 or Bluetooth 5.0, or any other iteration of the Bluetooth Standard. In embodiments that include BT functionality as shown for example in FIG. 12, the radio architecture 1200 may be configured to establish a BT synchronous connection oriented (SCO) link and or a BT low energy (BT LE) link. In some of the embodiments that include

functionality, the radio architecture 1200 may be configured to establish an extended SCO (eSCO) link for BT communications, although the scope of the embodiments is not limited in this respect. In some of these embodiments that include a BT functionality, the radio architecture may be configured to engage in a BT Asynchronous Connection-Less (ACL) communications, although the scope of the embodiments is not limited in this respect. In some embodiments, as shown in FIG. 12, the functions of a BT radio card and WLAN radio card may be combined on a single wireless radio card, such as single wireless radio card 1202, although embodiments are not so limited, and include within their scope discrete WLAN and BT radio cards

In some embodiments, the radio-architecture 1200 may include other radio cards, such as a cellular radio card configured for cellular (e.g., 12GPP such as LTE, LTE-Advanced or 5G communications).

In some IEEE 802.11 embodiments, the radio architecture 1200 may be configured for communication over various channel bandwidths including bandwidths having center frequencies of about 900 MHz, 11.4 GHz, 5 GHz, and bandwidths of about 10 MHz, 11 MHz, 11.5 MHz, 13 MHz, 5MHz, 8 MHz, 100 MHz, 106 MHz, 110 MHz, 130MHz, 80MHz (with contiguous bandwidths) or 80+80MHz (160MHz) (with non-contiguous bandwidths). In some embodiments, a 1420 MHz channel bandwidth may be used. The scope of the embodiments is not limited with respect to the above center frequencies however.

FIG. 13 illustrates FEM circuitry 1300 in accordance with some embodiments. The FEM circuitry 1300 is one example of circuitry that may be suitable for use as the WLAN and/or BT FEM circuitry 1204a/104b (FIG. 12), although other circuitry configurations may also be suitable.

In some embodiments, the FEM circuitry 1300 may include a TX/RX switch 1302 to switch between transmit mode and receive mode operation. The FEM circuitry 1300 may include a receive signal path and a transmit signal path. The receive signal path of the FEM circuitry 1300 may include a low-noise amplifier (LNA) 1306 to amplify received RF signals 1303 and provide the amplified received RF signals 1307 as an output (e.g., to the radio IC circuitry 1206 (FIG. 12)). The transmit signal path of the circuitry 1300 may include a power amplifier (PA) to amplify input RF signals 1309 (e.g., provided by the radio IC circuitry 1206), and one or more filters 1312, such as band-pass filters (BPFs), low-pass filters (LPFs) or other types of filters, to generate RF signals 1315 for subsequent transmission (e.g., by one or more of the antennas 1201 (FIG. 12)).

In some dual-mode embodiments for Wi-Fi communication, the FEM circuitry 1300 may be configured to operate in either the 11.4 GHz frequency spectrum or the 5 GHz frequency spectrum. In these embodiments, the receive signal path of the FEM circuitry 1300 may include a receive signal path duplexer 1304 to separate the signals from each spectrum as well as provide a separate LNA 1306 for each spectrum as shown. In these embodiments, the transmit signal path of the FEM circuitry 1300 may also include a power amplifier 1310 and a filter 1312, such as a BPF, a LPF or another type of filter for each frequency spectrum and a transmit signal path duplexer 1314 to provide the signals of one of the different spectrums onto a single transmit path for subsequent transmission by the one or more of the antennas 1201 (FIG. 12). In some embodiments, BT communications may utilize the 11.4 GHZ signal paths and may utilize the same FEM circuitry 1300 as the one used for WLAN communications.

FIG. 14 illustrates radio IC circuitry 1400 in accordance with some embodiments. The radio IC circuitry 1400 is one example of circuitry that may be suitable for use as the WLAN or BT radio IC circuitry 1206a/1206b (FIG. 12), although other circuitry configurations may also be suitable.

In some embodiments, the radio IC circuitry 1400 may include a receive signal path and a transmit signal path. The receive signal path of the radio IC circuitry 1400 may include at least mixer circuitry 1402, such as, for example, down-conversion mixer circuitry, amplifier circuitry 1406 and filter circuitry 1408. The transmit signal path of the radio IC circuitry 1400 may include at least filter circuitry 1412 and mixer circuitry 1414, such as, for example, up-conversion mixer circuitry. Radio IC circuitry 1400 may also include synthesizer circuitry 1404 for synthesizing a frequency 1405 for use by the mixer circuitry 1402 and the mixer circuitry 1414. The mixer circuitry 1402 and/or 1414 may each, according to some embodiments, be configured to provide direct conversion functionality. The latter type of circuitry presents a much simpler architecture as compared with standard super-heterodyne mixer circuitries, and any flicker noise brought about by the same may be alleviated for example through the use of OFDM modulation. FIG. 14 illustrates only a simplified version of a radio IC circuitry, and may include, although not shown, embodiments where each of the depicted circuitries may include more than one component. For instance, mixer circuitry 1420 and/or 1414 may each include one or more mixers, and filter circuitries 1408 and/or 1412 may each include one or more filters, such as one or more BPFs and/or LPFs according to application needs. For example, when mixer circuitries are of the direct-conversion type, they may each include two or more mixers.

In some embodiments, mixer circuitry 1402 may be configured to down-convert RF signals 1307 received from the FEM circuitry 1204 (FIG. 12) based on the synthesized frequency 1405 provided by synthesizer circuitry 1404. The amplifier circuitry 1406 may be configured to amplify the down- converted signals and the filter circuitry 1408 may include a LPF configured to remove unwanted signals from the down-converted signals to generate output baseband signals 1407. Output baseband signals 1407 may be provided to the baseband processing circuitry 1208 (FIG. 12) for further processing. In some embodiments, the output baseband signals 1407 may be zero-frequency baseband signals, although this is not a requirement. In some embodiments, mixer circuitry 1402 may comprise passive mixers, although the scope of the embodiments is not limited in this respect.

In some embodiments, the mixer circuitry 1414 may be configured to up-convert input baseband signals 1411 based on the synthesized frequency 1405 provided by the synthesizer circuitry 1404 to generate RF output signals 1309 for the FEM circuitry 1204. The baseband signals 1411 may be provided by the baseband processing circuitry 1208 and may be filtered by filter circuitry 1412. The filter circuitry 1412 may include a LPF or a BPF, although the scope of the embodiments is not limited in this respect.

In some embodiments, the mixer circuitry 1402 and the mixer circuitry 1414 may each include two or more mixers and may be arranged for quadrature down-conversion and/or up-conversion respectively with the help of synthesizer 1404. In some embodiments, the mixer circuitry 1402 and the mixer circuitry 1414 may each include two or more mixers each configured for image rejection (e.g., Hartley image rejection). In some embodiments, the mixer circuitry 1402 and the mixer circuitry 1414 may be arranged for direct down-conversion and/or direct up-conversion, respectively. In some embodiments, the mixer circuitry 1402 and the mixer circuitry 1414 may be configured for super-heterodyne operation, although this is not a requirement.

Mixer circuitry 1402 may comprise, according to one embodiment: quadrature passive mixers (e.g., for the in-phase (I) and quadrature phase (Q) paths). In such an embodiment, RF input signal 1307 from FIG. 14 may be down-converted to provide I and Q baseband output signals to be sent to the baseband processor

Quadrature passive mixers may be driven by zero and ninety degree time-varying LO switching signals provided by a quadrature circuitry which may be configured to receive a LO frequency (fLO) from a local oscillator or a synthesizer, such as LO frequency 1405 of synthesizer 1404 (FIG. 14). In some embodiments, the LO frequency may be the carrier frequency, while in other embodiments, the LO frequency may be a fraction of the carrier frequency (e.g., one-half the carrier frequency, one-third the carrier frequency). In some embodiments, the zero and ninety degree time-varying switching signals may be generated by the synthesizer, although the scope of the embodiments is not limited in this respect.

In some embodiments, the LO signals may differ in duty cycle (the percentage of one period in which the LO signal is high) and/or offset (the difference between start points of the period). In some embodiments, the LO signals may have a 115% duty cycle and a 50% offset. In some embodiments, each branch of the mixer circuitry (e.g., the in-phase (I) and quadrature phase (Q) path) may operate at a 115% duty cycle, which may result in a significant reduction is power consumption.

The RF input signal 1307 (FIG. 13) may comprise a balanced signal, although the scope of the embodiments is not limited in this respect. The I and Q baseband output signals may be provided to low-nose amplifier, such as amplifier circuitry 1406 (FIG. 14) or to filter circuitry 1408 (FIG. 14).

In some embodiments, the output baseband signals 1407 and the input baseband signals 1411 may be analog baseband signals, although the scope of the embodiments is not limited in this respect. In some alternate embodiments, the output baseband signals 1407 and the input baseband signals 1411 may be digital baseband signals. In these alternate embodiments, the radio IC circuitry may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) circuitry.

In some dual-mode embodiments, a separate radio IC circuitry may be provided for processing signals for each spectrum, or for other spectrums not mentioned here, although the scope of the embodiments is not limited in this respect.

In some embodiments, the synthesizer circuitry 1404 may be a fractional -N synthesizer or a fractional N/N+l synthesizer, although the scope of the embodiments is not limited in this respect as other types of frequency synthesizers may be suitable. For example, synthesizer circuitry 1404 may be a delta-sigma synthesizer, a frequency multiplier, or a synthesizer comprising a phase-locked loop with a frequency divider. According to some

embodiments, the synthesizer circuitry 1404 may include digital synthesizer circuitry. An advantage of using a digital synthesizer circuitry is that, although it may still include some analog components, its footprint may be scaled down much more than the footprint of an analog synthesizer circuitry. In some embodiments, frequency input into synthesizer circuity 1404 may be provided by a voltage controlled oscillator (VCO), although that is not a requirement. A divider control input may further be provided by either the baseband processing circuitry 1208 (FIG. 12) or the application processor 1210 (FIG. 12) depending on the desired output frequency 1405. In some embodiments, a divider control input (e.g., N) may be determined from a lookup table (e.g., within a Wi-Fi card) based on a channel number and a channel center frequency as determined or indicated by the application processor 1210.

In some embodiments, synthesizer circuitry 1404 may be configured to generate a carrier frequency as the output frequency 1405, while in other embodiments, the output frequency 1405 may be a fraction of the carrier frequency (e.g., one-half the carrier frequency, one-third the carrier frequency). In some embodiments, the output frequency 1405 may be a LO frequency (fLO).

FIG. 15 illustrates a functional block diagram of baseband processing circuitry 1500 in accordance with some embodiments. The baseband processing circuitry 1500 is one example of circuitry that may be suitable for use as the baseband processing circuitry 1208 (FIG. 12), although other circuitry configurations may also be suitable. The baseband processing circuitry 1500 may include a receive baseband processor (RX BBP) 1502 for processing receive baseband signals 1409 provided by the radio IC circuitry 1206 (FIG. 12) and a transmit baseband processor (TX BBP) 1504 for generating transmit baseband signals 1411 for the radio IC circuitry 1206. The baseband processing circuitry 1500 may also include control logic 1506 for coordinating the operations of the baseband processing circuitry 1500.

In some embodiments (e.g., when analog baseband signals are exchanged between the baseband processing circuitry 1500 and the radio IC circuitry 1206), the baseband processing circuitry 1500 may include ADC 1510 to convert analog baseband signals received from the radio IC circuitry 1206 to digital baseband signals for processing by the RX BBP 1502. In these embodiments, the baseband processing circuitry 1500 may also include DAC 1512 to convert digital baseband signals from the TX BBP 1504 to analog baseband signals.

In some embodiments that communicate OFDM signals or OFDMA signals, such as through baseband processor 1208a, the transmit baseband processor 1504 may be configured to generate OFDM or OFDMA signals as appropriate for transmission by performing an inverse fast Fourier transform (IFFT). The receive baseband processor 1502 may be configured to process received OFDM signals or OFDMA signals by performing an FFT. In some embodiments, the receive baseband processor 1502 may be configured to detect the presence of an OFDM signal or OFDMA signal by performing an autocorrelation, to detect a preamble, such as a short preamble, and by performing a cross-correlation, to detect a long preamble. The preambles may be part of a predetermined frame structure for Wi-Fi communication.

Referring back to FIG. 12, in some embodiments, the antennas 1201 (FIG. 12) may each comprise one or more directional or omnidirectional antennas, including, for example, dipole antennas, monopole antennas, patch antennas, loop antennas, microstrip antennas or other types of antennas suitable for transmission of RF signals. In some multiple-input multiple-output (MFMO) embodiments, the antennas may be effectively separated to take advantage of spatial diversity and the different channel characteristics that may result. Antennas 1201 may each include a set of phased-array antennas, although embodiments are not so limited.

Although the radio-architecture 1200 is illustrated as having several separate functional elements, one or more of the functional elements may be combined and may be implemented by combinations of software-configured elements, such as processing elements including digital signal processors (DSPs), and/or other hardware elements. For example, some elements may comprise one or more microprocessors, DSPs, field-programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), radio-frequency integrated circuits (RFICs) and combinations of various hardware and logic circuitry for performing at least the functions described herein. In some embodiments, the functional elements may refer to one or more processes operating on one or more processing elements.

FIG. 16 is a block diagram of an example processor platform 1600 capable of executing the instructions of FIG. 5. The processor platform 1600 could also be used to implement the features of FIG. 10. The processor platform 1600 can be, for example, a server, a personal computer, a mobile device (e.g., a cell phone, a smart phone, a tablet such as an iPad™), a personal digital assistant (PDA), an Internet appliance, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a gaming console, a personal video recorder, a set top box, or any other type of computing device.

The processor platform 1600 of the illustrated example includes a processor 1612. The processor 1612 of the illustrated example is hardware. For example, the processor 1612 can be implemented by one or more integrated circuits, logic circuits, microprocessors or controllers from any desired family or manufacturer. The hardware processor may be a

semiconductor based (e.g., silicon based) device. In this example, the processor 1612 implements the beacon receiver 402, the parameter extractor 404, the cycle handler 406, and the transmission controller 408.

The processor 1612 of the illustrated example includes a local memory 1613 (e.g., a cache). The processor 1612 of the illustrated example is in communication with a main memory including a volatile memory 1614 and a non-volatile memory 1616 via a bus 1618. The volatile memory 1614 may be implemented by Synchronous Dynamic Random Access Memory (SDRAM), Dynamic Random Access Memory (DRAM), RAMBUS Dynamic Random Access Memory (RDRAM) and/or any other type of random access memory device. The non-volatile memory 1616 may be implemented by flash memory and/or any other desired type of memory device. Access to the main memory 1614, 1616 is controlled by a memory controller.

The processor platform 1600 of the illustrated example also includes an interface circuit 1620. The interface circuit 1620 may be implemented by any type of interface standard, such as an Ethernet interface, a universal serial bus (USB), and/or a PCI express interface.

In the illustrated example, one or more input devices 1622 are connected to the interface circuit 1620. The input device(s) 1622 permit(s) a user to enter data and/or commands into the processor 1612. The input device(s) can be implemented by, for example, an audio sensor, a microphone, a camera (still or video), a keyboard, a button, a mouse, a touchscreen, a trackpad, a trackball, isopoint and/or a voice recognition system. One or more output devices 1624 are also connected to the interface circuit 1620 of the illustrated example. The output devices 1624 can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display, a cathode ray tube display (CRT), a touchscreen, a tactile output device, a printer and/or speakers). The interface circuit 1620 of the illustrated example, thus, typically includes a graphics driver card, a graphics driver chip and/or a graphics driver processor.

The interface circuit 1620 of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem and/or network interface card to facilitate exchange of data with external machines (e.g., computing devices of any kind) via a network 1626 (e.g., an Ethernet connection, a digital subscriber line (DSL), a telephone line, coaxial cable, a cellular telephone system, etc.).

The processor platform 1600 of the illustrated example also includes one or more mass storage devices 1628 for storing software and/or data. Examples of such mass storage devices 1628 include floppy disk drives, hard drive disks, compact disk drives, Blu-ray disk drives, RAID systems, and digital versatile disk (DVD) drives.

The coded instructions 1632 of FIG. 5 may be stored in the mass storage device 1628, in the volatile memory 1614, in the non-volatile memory 1616, and/or on a removable tangible computer readable storage medium such as a CD or DVD.

From the foregoing, it will be appreciated that example methods, apparatus and articles of manufacture have been disclosed that facilitate the implementation of TSN in Wi-Fi networks. In some examples, wireless devices are controlled to ensure that random access to communication channels is controlled to deterministically align transmissions with a control cycle time for the network. In some examples, communications are time synchronized across all STA to deterministically align wireless

communication (e.g., IEEE 802.11 wireless communication) to a deterministic control cycle across a network. Example 1 is a wireless device comprising memory and processing circuitry configured to: scan for a first beacon from a Wi-Fi access point, extract a target beacon transmission time and an absolute cycle number from the first beacon, determine a next beacon cycle number for the next beacon based on the absolute cycle number and the target beacon transmission time, and scan for a second beacon at the next beacon cycle number.

Example 2 includes the wireless device as defined in example 1, wherein the processing circuitry is configured to extract a cycle time from the first beacon.

Example 3 includes the wireless device as defined in example 2, wherein the processing circuitry is configured to synchronize the wireless device to the cycle time.

Example 4 includes the wireless device as defined in example 1, wherein the first beacon is transmitted by an access point.

Example 5 includes the wireless device as defined in example 4, wherein the access point transmits a third beacon after a cycle transmission offset.

Example 6 includes the wireless device as defined in example 5, wherein the processing circuitry is configured to, after waiting for a cycle reception offset, initiate a wireless receiver to receive the third beacon.

Example 7 includes the wireless device as defined in example 5, wherein the processing circuitry is configured to, after waiting for a cycle reception offset, tune a wireless receiver to an operating channel to receive the third beacon.

Example 8 includes the wireless device as defined in example 1, wherein the first beacon is received during a first cycle, further including transmitting first data during a second cycle, wherein an access point instructs a second wireless device to enable a receiver to receive the first data during the second cycle.

Example 9 includes the wireless device as defined in example 8, wherein the access point instructs the second wireless device to transmit second data during a third cycle. Example 10 includes the wireless device as defined in example 1, wherein the first beacon is received during a first cycle, wherein the processing circuitry is configured to transmit first data during a second cycle on a first channel, wherein an access point instructs a second wireless device to tune a receiver to the first channel to receive the first data during the second cycle, the access point instructs a third wireless device to transmit second data on a second channel during the second cycle, and the access point instructs a fourth wireless device to tune a receiver to the second channel to receive the second data during the second cycle.

Example 11 includes the wireless device as defined in example 1, wherein the processing circuitry is further configured to transmit information about an application to an access point, wherein the access point determines the cycle time based on the information about the application.

Example 12 is a method for time sensitive network communication in wireless networks, the method comprising: scanning, at a wireless device, for a first beacon from a Wi-Fi access point, extracting, at the wireless device, a target beacon transmission time and an absolute cycle number from the first beacon, determining, at the wireless device, a next beacon cycle number for the next beacon based on the absolute cycle number and the target beacon transmission time, and recording, at the wireless device, a second beacon at the next beacon cycle number.

Example 13 includes the method as defined in example 12, further including extracting a cycle time from the first beacon.

Example 14 includes the method as defined in example 13, further including synchronizing the wireless device to the cycle time.

Example 15 includes the method as defined in example 12, wherein the first beacon is transmitted by an access point.

Example 16 includes the method as defined in example 15, wherein the access point transmits a third beacon after a cycle transmission offset.

Example 17 includes the method as defined in example 16, further including after waiting for a cycle reception offset, initiating a wireless receiver to receive the third beacon. Example 18 includes the method as defined in example 16, further including after waiting for a cycle reception offset, tuning a wireless receiver to an operating channel to receive the third beacon.

Example 19 includes the method as defined in example 12, wherein the first beacon is received during a first cycle, further including transmitting first data during a second cycle, wherein an access point instructs a second wireless device to enable a receiver to receive the first data during the second cycle.

Example 20 includes the method as defined in example 19, wherein the access point instructs the second wireless device to transmit second data during a third cycle.

Example 21 includes the method as defined in example 12, wherein the first beacon is received during a first cycle, further including transmitting, by the wireless device, first data during a second cycle on a first channel, wherein an access point instructs a second wireless device to tune a receiver to the first channel to receive the first data during the second cycle, the access point instructs a third wireless device to transmit second data on a second channel during the second cycle, and the access point instructs a fourth wireless device to tune a receiver to the second channel to receive the second data during the second cycle.

Example 22 includes the method as defined in example 12, further including transmitting information about an application to an access point, wherein the access point determines the cycle time based on the information about the application.

Example 23 is a non-transitory computer readable medium comprising instructions that, when executed, cause a wireless device to at least: scan for a first beacon from a Wi-Fi access point, extract a target beacon transmission time and an absolute cycle number from the first beacon, determine a next beacon cycle number for the next beacon based on the absolute cycle number and the target beacon transmission time, and scan for a second beacon at the next beacon cycle number. Example 24 includes the non-transitory computer readable medium as defined in example 23, wherein the instructions, when executed, cause the wireless device to extract a cycle time from the first beacon.

Example 25 includes the non-transitory computer readable medium as defined in example 24, wherein the instructions, when executed, cause the wireless device to synchronize the wireless device to the cycle time.

Example 26 includes the non-transitory computer readable medium as defined in example 23, wherein the first beacon is transmitted by an access point.

Example 27 includes the non-transitory computer readable medium as defined in example 26, wherein the access point transmits a third beacon after a cycle transmission offset.

Example 28 includes the non-transitory computer readable medium as defined in example 27, wherein the instructions, when executed, cause the wireless device to, after waiting for a cycle reception offset, initiate a wireless receiver to receive the third beacon.

Example 29 includes the non-transitory computer readable medium as defined in example 27, wherein the instructions, when executed, cause the wireless device to, after waiting for a cycle reception offset, tune a wireless receiver to an operating channel to receive the third beacon.

Example 30 includes the non-transitory computer readable medium as defined in example 23, wherein the first beacon is received during a first cycle, wherein the instructions, when executed, cause the wireless device to transmit first data during a second cycle, wherein an access point instructs a second wireless device to enable a receiver to receive the first data during the second cycle.

Example 31 includes the non-transitory computer readable medium as defined in example 30, wherein the access point instructs the second wireless device to transmit second data during a third cycle.

Example 32 includes the non-transitory computer readable medium as defined in example 23, wherein the first beacon is received during a first cycle, wherein the instructions, when executed, cause the wireless device to transmit first data during a second cycle on a first channel, wherein an access point instructs a second wireless device to tune a receiver to the first channel to receive the first data during the second cycle, the access point instructs a third wireless device to transmit second data on a second channel during the second cycle, and the access point instructs a fourth wireless device to tune a receiver to the second channel to receive the second data during the second cycle.

Example 33 includes the non-transitory computer readable medium as defined in example 23, wherein the instructions, when executed, cause the wireless device to transmit information about an application to an access point, wherein the access point determines the cycle time based on the information about the application.

Example 34 is an apparatus for time sensitive network communication in wireless networks, the apparatus comprising: means for scanning for a first beacon from a Wi-Fi access point, means for extracting a target beacon transmission time and an absolute cycle number from the first beacon, means for determining a next beacon cycle number for the next beacon based on the absolute cycle number and the target beacon transmission time, and means for recording a second beacon at the next beacon cycle number.

Example 35 includes the apparatus as defined in example 34, further including means for extracting a cycle time from the first beacon.

Example 36 is a system comprising: a Wi-Fi access point to transmit a first beacon, and a wireless device to: scan for the first beacon, extract a target beacon transmission time and an absolute cycle number from the first beacon, determine a next beacon cycle number for the next beacon based on the absolute cycle number and the target beacon transmission time, and scan for a second beacon at the next beacon cycle number.

Example 37 includes the system as defined in example 36, wherein the wireless device is to extract a cycle time from the first beacon.

Although certain example methods, apparatus and articles of manufacture have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus and articles of manufacture fairly falling within the scope of the claims of this patent.