VIDEO CODING

CROSS-REFERENCE TO RELATED APPLICATION [0001] The present application claims priority to U.S. Provisional Application No. 63/007,355, entitled “Signaling of Syntax Elements in Video Coding,” filed on April 8, 2020, U.S. Provisional Application No. 63/009,404, entitled “Signaling of Syntax Elements in Video Coding,” filed on April 13, 2020, U.S. Provisional Application No. 63/010/005, entitled “Signaling of Syntax Elements in Video Coding,” filed on April 14, 2020, U.S. Provisional Application No. 60/010,619, entitled “Signaling of Syntax Elements in Video Coding,” filed on April 15, 2020, and U.S. Provisional Application No. 63/015,663, entitled “Signaling of Syntax Elements in Video Coding,” filed on April 26, 2020, the entirety of all of which is incorporated by reference for all purposes.

FIELD

[0002] The present disclosure relates to video coding and compression, and in particular but not limited to, methods and apparatuses for signaling of syntax elements in video coding.

BACKGROUND

[0003] Various video coding techniques may be used to compress video data. Video coding is performed according to one or more video coding standards. For example, video coding standards include versatile video coding (VVC), joint exploration test model (JEM), high- efficiency video coding (H.265/HEVC), advanced video coding (H.264/AVC), moving picture experts group (MPEG) coding, or the like. Video coding generally utilizes prediction methods (e.g., inter-prediction, intra-prediction, or the like) that take advantage of redundancy present in video images or sequences. An important goal of video coding techniques is to compress video data into a form that uses a lower bit rate, while avoiding or minimizing degradations to video quality.

SUMMARY

[0004] The present disclosure provides examples of techniques relating to signaling of syntax elements in video coding. [0005] According to a first aspect of the present disclosure, there is provided a method for video coding. The method includes that a decoder determines whether a disable flag is present in a picture header (PH) associated with a picture, wherein the disable flag specifies whether a coding tool is disabled in one or more slices associated with the PH. Additionally, the method includes that the decoder infers value of the disable flag according to one or more enable flags signaled in sequence parameter sets (SPS) of the picture in response to determining that the disable flag is not present in the PH.

[0006] According to a second aspect of the present disclosure, there is provided a method for video coding. The method includes that a decoder determines whether a flag is present in a PH associated with a picture and the flag specifies whether the picture used for temporal motion vector prediction (TMVP) is derived from a reference picture list from a plurality of reference picture lists associated with the picture. Additionally, the method includes that the decoder infers value of the flag according to a number of reference pictures in the reference picture list in response to determining that the flag is not present in the PH.

[0007] According to a third aspect of the present disclosure, there is provided a method for video coding. The method includes that a decoder determines whether a flag is present in a PH associated with a picture, the flag specifies a number of weights signaled in a reference picture list according to a first weighted prediction (WP) flag in picture parameter sets (PPS) of the picture and a second WP flag in the PH of the picture, and the flag is in a WP syntax associated with the picture. Additionally, the method includes that the decoder infers value of the flag according to a number of reference pictures in a reference picture list from a plurality of refence picture lists associated with the picture in response to determining that the flag is not present in the PH.

[0008] According to a fourth aspect of the present disclosure, there is provided a method for video coding. The method includes that a decoder uses an enabled flag to specify whether one or more temporal motion vector predictors used for inter prediction for one or more slices associated with a PH of a picture. Additionally, the method includes that the decoder constrains value of the enabled flag according to a plurality of offsets applied to a size of the picture for scaling ratio calculation.

[0009] According to a fifth aspect of the present disclosure, there is provided an apparatus for video coding. The apparatus includes one or more processors and a memory configured to store instructions executable by the one or more processors. The one or more processors, upon execution of the instructions, are configured to perform the method for video coding according to the first aspect of the present disclosure.

[0010] According to a sixth aspect of the present disclosure, there is provided an apparatus for video coding. The apparatus includes one or more processors and a memory configured to store instructions executable by the one or more processors. The one or more processors, upon execution of the instructions, are configured to perform the method for video coding according to the second aspect of the present disclosure.

[0011] According to a seventh aspect of the present disclosure, there is provided an apparatus for video coding. The apparatus includes one or more processors and a memory configured to store instructions executable by the one or more processors. The one or more processors, upon execution of the instructions, are configured to perform the method for video coding according to the third aspect of the present disclosure.

[0012] According to an eighth aspect of the present disclosure, there is provided an apparatus for video coding. The apparatus includes one or more processors and a memory configured to store instructions executable by the one or more processors. The one or more processors, upon execution of the instructions, are configured to perform the method for video coding according to the fourth aspect of the present disclosure.

[0013] According to a ninth aspect of the present disclosure, there is provided a non- transitory computer readable storage medium for video coding storing computer-executable instructions. The instructions, when executed by one or more computer processors, causing the one or more computer processors to perform the method for video coding according to the first aspect of the present disclosure.

[0014] According to a tenth aspect of the present disclosure, there is provided a non- transitory computer readable storage medium for video coding storing computer-executable instructions. The instructions, when executed by one or more computer processors, causing the one or more computer processors to perform the method for video coding according to the second aspect of the present disclosure.

[0015] According to an eleventh aspect of the present disclosure, there is provided a non- transitory computer readable storage medium for video coding storing computer-executable instructions. The instructions, when executed by one or more computer processors, causing the one or more computer processors to perform the method for video coding according to the third aspect of the present disclosure. [0016] According to a twelfth aspect of the present disclosure, there is provided a non- transitory computer readable storage medium for video coding storing computer-executable instructions. The instructions, when executed by one or more computer processors, causing the one or more computer processors to perform the method for video coding according to the fourth aspect of the present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

[0017] A more particular description of the examples of the present disclosure will be rendered by reference to specific examples illustrated in the appended drawings. Given that these drawings depict only some examples and are not therefore considered to be limiting in scope, the examples will be described and explained with additional specificity and details through the use of the accompanying drawings.

[0018] FIG. 1 is a block diagram illustrating an exemplary video encoder in accordance with some implementations of the present disclosure.

[0019] FIG. 2 is a block diagram illustrating an exemplary video decoder in accordance with some implementations of the present disclosure.

[0020] FIG. 3 illustrates an example of a picture divided into multiple coding tree units (CTUs) in accordance with some implementations of the present disclosure.

[0021] FIGS. 4A-4D are schematic diagrams illustrating multi -type tree splitting modes in accordance with some implementations of the present disclosure.

[0022] FIG. 5 is a block diagram illustrating an exemplary apparatus for video coding in accordance with some implementations of the present disclosure.

[0023] FIG. 6 is a flowchart illustrating an exemplary process of video coding in accordance with some implementations of the present disclosure.

[0024] FIG. 7 is a flowchart illustrating an exemplary process of video coding in accordance with some implementations of the present disclosure.

[0025] FIG. 8 is a flowchart illustrating an exemplary process of video coding in accordance with some implementations of the present disclosure.

[0026] FIG. 9 is a flowchart illustrating an exemplary process of video coding in accordance with some implementations of the present disclosure. DETAILED DESCRIPTION

[0027] Reference will now be made in detail to specific implementations, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous non-limiting specific details are set forth in order to assist in understanding the subject matter presented herein. But it will be apparent to one of ordinary skill in the art that various alternatives may be used. For example, it will be apparent to one of ordinary skill in the art that the subject matter presented herein can be implemented on many types of electronic devices with digital video capabilities.

[0028] Reference throughout this specification to “one embodiment,” “an embodiment,”

“an example,” “some embodiments,” “some examples,” or similar language means that a particular feature, structure, or characteristic described is included in at least one embodiment or example. Features, structures, elements, or characteristics described in connection with one or some embodiments are also applicable to other embodiments, unless expressly specified otherwise.

[0029] Throughout the disclosure, the terms “first,” “second,” “third,” and etc. are all used as nomenclature only for references to relevant elements, e.g. devices, components, compositions, steps, and etc., without implying any spatial or chronological orders, unless expressly specified otherwise. For example, a “first device” and a “second device” may refer to two separately formed devices, or two parts, components or operational states of a same device, and may be named arbitrarily.

[0030] The terms “module,” “sub-module,” “circuit,” “sub-circuit,” “circuitry,” “sub circuitry,” “unit,” or “sub-unit” may include memory (shared, dedicated, or group) that stores code or instructions that can be executed by one or more processors. A module may include one or more circuits with or without stored code or instructions. The module or circuit may include one or more components that are directly or indirectly connected. These components may or may not be physically attached to, or located adjacent to, one another.

[0031] As used herein, the term “if’ or “when” may be understood to mean “upon” or “in response to” depending on the context. These terms, if appear in a claim, may not indicate that the relevant limitations or features are conditional or optional. For example, a method may comprise steps of: i) when or if condition X is present, function or action X’ is performed, and ii) when or if condition Y is present, function or action Y’ is performed. The method may be implemented with both the capability of performing function or action X’, and the capability of performing function or action Y\ Thus, the functions X’ and Y’ may both be performed, at different times, on multiple executions of the method.

[0032] A unit or module may be implemented purely by software, purely by hardware, or by a combination of hardware and software. In a pure software implementation, for example, the unit or module may include functionally related code blocks or software components, that are directly or indirectly linked together, so as to perform a particular function.

[0033] FIG. 1 shows a block diagram of illustrating an exemplary block-based hybrid video encoder 100 which may be used in conjunction with many video coding standards using block-based processing. In the encoder 100, a video frame is partitioned into a plurality of video blocks for processing. For each given video block, a prediction is formed based on either an inter prediction approach or an intra prediction approach. In inter prediction, one or more predictors are formed through motion estimation and motion compensation, based on pixels from previously reconstructed frames. In intra prediction, predictors are formed based on reconstructed pixels in a current frame. Through mode decision, a best predictor may be chosen to predict a current block.

[0034] A prediction residual, representing the difference between a current video block and its predictor, is sent to a Transform circuitry 102. Transform coefficients are then sent from the Transform circuitry 102 to a Quantization circuitry 104 for entropy reduction. Quantized coefficients are then fed to an Entropy Coding circuitry 106 to generate a compressed video bitstream. As shown in FIG. 1, prediction-related information 110 from an inter prediction circuitry and/or an Intra Prediction circuitry 112, such as video block partition info, motion vectors, reference picture index, and intra prediction mode, are also fed through the Entropy Coding circuitry 106 and saved into a compressed video bitstream 114.

[0035] In the encoder 100, decoder-related circuitries are also needed in order to reconstruct pixels for the purpose of prediction. First, a prediction residual is reconstructed through an Inverse Quantization 116 and an Inverse Transform circuitry 118. This reconstructed prediction residual is combined with a Block Predictor 120 to generate un- filtered reconstructed pixels for a current video block.

[0036] Intra prediction (also referred to as “spatial prediction”) uses pixels from the samples of already coded neighboring blocks (which are called reference samples) in the same video picture and/or slice to predict the current video block. Spatial prediction reduces spatial redundancy inherent in the video signal. [0037] Inter prediction (also referred to as “temporal prediction”) uses reconstructed pixels from already-coded video pictures to predict the current video block. Temporal prediction reduces temporal redundancy inherent in the video signal. Temporal prediction signal for a given coding unit (CU) or coding block is usually signaled by one or more motion vectors (MVs) which indicate the amount and the direction of motion between the current CU and its temporal reference. Further, if multiple reference pictures are supported, one reference picture index is additionally sent, which is used to identify from which reference picture in the reference picture store the temporal prediction signal comes.

[0038] After spatial and/or temporal prediction is performed, an intra/inter mode decision circuitry 121 in the encoder 100 chooses the best prediction mode, for example based on the rate-distortion optimization method. The block predictor 120 is then subtracted from the current video block; and the resulting prediction residual is de-correlated using the transform circuitry 102 and the quantization circuitry 104. The resulting quantized residual coefficients are inverse quantized by the inverse quantization circuitry 116 and inverse transformed by the inverse transform circuitry 118 to form the reconstructed residual, which is then added back to the prediction block to form the reconstructed signal of the CU. Further, in-loop filtering 115, such as a deblocking filter, a sample adaptive offset (SAO), and/or an adaptive in-loop filter (ALF) may be applied on the reconstructed CU before it is put in the reference picture store of the picture buffer 117 and used to code future video blocks. To form the output video bitstream 114, coding mode (inter or intra), prediction mode information, motion information, and quantized residual coefficients are all sent to the entropy coding unit 106 to be further compressed and packed to form the bit-stream.

[0039] For example, a deblocking filter is available in AVC, HEVC as well as the now- current version of VVC. In HEVC, an additional in-loop filter called SAO (sample adaptive offset) is defined to further improve coding efficiency. In the now-current version of the VVC standard, yet another in-loop filter called ALF (adaptive loop filter) is being actively investigated, and it has a good chance of being included in the final standard.

[0040] These in-loop filter operations are optional. Performing these operations helps to improve coding efficiency and visual quality. They may also be turned off as a decision rendered by the encoder 100 to save computational complexity.

[0041] It should be noted that intra prediction is usually based on unfiltered reconstructed pixels, while inter prediction is based on filtered reconstructed pixels if these filter options are turned on by the encoder 100. [0042] FIG. 2 is a block diagram illustrating an exemplary block-based video decoder 200 which may be used in conjunction with many video coding standards. This decoder 200 is similar to the reconstruction-related section residing in the encoder 100 of FIG. 1. In the decoder 200, an incoming video bitstream 201 is first decoded through an Entropy Decoding 202 to derive quantized coefficient levels and prediction-related information. The quantized coefficient levels are then processed through an Inverse Quantization 204 and an Inverse Transform 206 to obtain a reconstructed prediction residual. A block predictor mechanism, implemented in an Intra/inter Mode Selector 212, is configured to perform either an Intra Prediction 208, or a Motion Compensation 210, based on decoded prediction information. A set of unfiltered reconstructed pixels are obtained by summing up the reconstructed prediction residual from the Inverse Transform 206 and a predictive output generated by the block predictor mechanism, using a summer 214.

[0043] The reconstructed block may further go through an In-Loop Filter 209 before it is stored in a Picture Buffer 213 which functions as a reference picture store. The reconstructed video in the Picture Buffer 213 may be sent to drive a display device, as well as used to predict future video blocks. In situations where the In-Loop Filter 209 is turned on, a filtering operation is performed on these reconstructed pixels to derive a final reconstructed Video Output 222.

[0044] Video coding/decoding standards mentioned above, such as VVC, JEM, HEVC, MPEG-4, Part 10, are conceptually similar. For example, they all use block-based processing. Block partitioning schemes in some standards are elaborated below.

Versatile Video Coding (VVC1

[0045] At the 10th JVET meeting, held April 10-20, 2018, San Diego, US, JVET defined the first draft of Versatile Video Coding (VVC) and the VVC Test Model 1 (VTM1) as its reference software implementation. It was decided to include a quadtree with a nested multi type tree as the initial new coding feature of VVC. The multi -type tree is a coding block partition structure including both binary and ternary split. Since then the reference software VTM, with both encoding and decoding process implemented, has been developed and updated through the following JVET meetings.

[0046] In VVC, a picture of an input video is partitioned into blocks called CTUs. A CTU is split into CUs using a quadtree with a nested multi-type tree structure, with a CU defining a region of pixels sharing the same prediction mode (e.g. intra or inter). The term ‘unit’ may define a region of an image covering all components such as luma and chroma. The term ‘block’ may be used to define a region covering a particular component (e.g. luma), and the blocks of different components (e.g. luma vs. chroma) may differ in spatial location when considering the chroma sampling format such as 4:2:0.

Partitioning of the Picture into CTUs

[0047] FIG. 3 illustrates an example of a picture 300 divided into multiple CTUs 302 in accordance with some implementations of the present disclosure.

[0048] Pictures are divided into a sequence of CTUs. The CTU concept is same to that of the HEVC. For a picture that has three sample arrays, a CTU consists of an N*N block of luma samples together with two corresponding blocks of chroma samples.

[0049] The maximum allowed size of the luma block in a CTU is specified to be 128x128 (although the maximum size of the luma transform blocks is 64x64).

Partitioning of the CTUs Using a Tree Structure

[0050] In HEVC, a CTU is split into CUs by using a quaternary -tree structure denoted as coding tree to adapt to various local characteristics. The decision whether to code a picture area using inter-picture (temporal) or intra-picture (spatial) prediction is made at the leaf CU level. Each leaf CU can be further split into one, two or four PUs according to the PU splitting type. Inside one PU, the same prediction process is applied and the relevant information is transmitted to the decoder on a PU basis. After obtaining the residual block by applying the prediction process based on the PU splitting type, a leaf CU can be partitioned into transform units (TUs) according to another quaternary -tree structure similar to the coding tree for the CU. One of key feature of the HEVC structure is that it has the multiple partition conceptions including CU, PU, and TU.

[0051] In VVC, a quadtree with nested multi-type tree using binary and ternary splits segmentation structure replaces the concepts of multiple partition unit types, i.e. it removes the separation of the CU, PU and TU concepts except as needed for CUs that have a size too large for the maximum transform length, and supports more flexibility for CU partition shapes. In the coding tree structure, a CU can have either a square or rectangular shape. A CTU is first partitioned by a quaternary tree (a.k.a. quadtree) structure. Then the quaternary tree leaf nodes can be further partitioned by a multi-type tree structure.

[0052] FIGS. 4A-4D are schematic diagrams illustrating multi -type tree splitting modes in accordance with some implementations of the present disclosure. As shown in FIGS. 4A-4D, there are four splitting types in multi-type tree structure, vertical binary splihing 402 (SPLIT BT VER), horizontal binary splitting 404 (SPLIT BT HOR), vertical ternary splitting 406 (SPLIT TT VER), and horizontal ternary splitting 408 (SPLIT TT HOR). The multi-type tree leaf nodes are called CUs, and unless the CU is too large for the maximum transform length, this segmentation is used for prediction and transform processing without any further partitioning. This means that, in most cases, the CU, PU, and TU have the same block size in the quadtree with nested multi-type tree coding block structure. The exception occurs when maximum supported transform length is smaller than the width or height of the colour component of the CU.

Syntax in VYC

[0053] In VVC, the first layer of bitstream of syntax signaling is the Network Abstraction Layer (NAL) where the bitstream is divided into a set of NAL units. Some NAL units signal common control parameters to the decoder, such as the Sequence Parameter Sets (SPS) and Picture Parameter Sets (PPS). Others contain video data. The Video Coding Layer (VCL) NAL units contain slices of coded video. A coded picture is called an access unit and can be encoded as one or more slices.

[0054] A coded video sequence starts with an Instantaneous Decoder Refresh (IDR) picture. All following video pictures are coded as slices. A new IDR picture signals that the previous video segment is ended, and a new one begins. Each NAL unit begins with a one- byte header followed by the Raw Byte Sequence Payload (RBSP). The RBSP contains encoded slices. Slices are binary coded, so they may be padded with zero bits to ensure that the length is an integer number of bytes. A slice consists of a slice header and slice data. Slice data are specified as a series of CUs.

[0055] The PH concept was adopted in the 16th JVET meeting to be transmitted once per picture as the first VCL NAL unit of a picture. It was also proposed to group some syntax elements previously in the slice header to this picture header. Syntax elements that functionally only need to be transmitted once per picture could be moved to the picture header instead of being transmitted multiple times in slices for a given picture.

[0056] In the VVC specification, the syntax tables specify a superset of the syntax of all allowed bitstreams. Additional constraints on the syntax may be specified, either directly or indirectly, in other clauses. Table 1 below is a syntax table of the slice header and picture header in VVC. The semantics of some syntax are also illustrated after the syntax table.

Table 1

Semantic of selected syntax elements

[0057] ph_temporal_mvp_enabled_flag specifies whether temporal motion vector predictors can be used for inter prediction for slices associated with the PH. If ph_temporal_mvp_enabled_flag is equal to 0, the syntax elements of the slices associated with the PH shall be constrained such that no temporal motion vector predictor is used in decoding of the slices. Otherwise if ph temporal mvp enabled flag is equal to 1, temporal motion vector predictors may be used in decoding of the slices associated with the PH. When not present, the value of ph temporal mvp enabled flag is inferred to be equal to 0. When no reference picture in the Decoded Picture Buffer (DPB) has the same spatial resolution as the current picture, the value of ph temporal mvp enabled flag shall be equal to 0.

[0058] The maximum number of subblock-based merging MVP candidates, MaxNumSubblockMergeCand, is derived as follows: if (sps_affme_enabled_flag)

MaxNumSubblockMergeCand = 5 - five_minus_max_num_subblock_merge_cand (87) else

MaxNumSubblockMergeCand=sps_sbtmvp_enabled_flag && ph_temporal_mvp_e nabled flag; where the value of MaxNumSubblockMergeCand shall be in the range of 0 to 5, inclusive. [0059] slice_collocated_from_10_flag equal to 1 specifies that the collocated picture used for temporal motion vector prediction is derived from reference picture list 0. slice_collocated_from_10_flag equal to 0 specifies that the collocated picture used for temporal motion vector prediction is derived from reference picture list 1.

[0060] When slice type is equal to B or P, ph temporal mvp enabled flag is equal to 1, and slice_collocated_from_10_flag is not present, the following applies:

- If rpl_info_in_ph_flag is equal to 1, slice collocated from lO flag is inferred to be equal to ph collocated from lO flag.

- Otherwise (rpl_info_in_ph_flag is equal to 0 and slice type is equal to P), the value of slice_collocated_from_10_flag is inferred to be equal to 1.

[0061] slice collocated ref idx specifies the reference index of the collocated picture used for temporal motion vector prediction.

[0062] When slice type is equal to P or when slice type is equal to B and slice_collocated_from_10_flag is equal to 1, slice_collocated_ref_idx refers to an entry in reference picture list 0, and the value of slice_collocated_ref_idx shall be in the range of 0 to NumRefldxActivef 0 ] - 1, inclusive.

[0063] When slice type is equal to B and slice collocated from lO flag is equal to 0, slice collocated ref idx refers to an entry in reference picture list 1, and the value of slice_collocated_ref_idx shall be in the range of 0 to NumRefldxActivef 1 ] - 1, inclusive. [0064] When slice collocated ref idx is not present, the following applies:

- If rpl_info_in_ph_flag is equal to 1, the value of slice collocated ref idx is inferred to be equal to ph collocated ref idx.

- Otherwise (rpl_info_in_ph_flag is equal to 0), the value of slice collocated ref idx is inferred to be equal to 0.

[0065] It is a requirement of bitstream conformance that the picture referred to by slice_collocated_ref_idx shall be the same for all slices of a coded picture.

[0066] It is a requirement of bitstream conformance that the values of pic width in luma samples and pic height in luma samples of the reference picture referred to by slice collocated ref idx shall be equal to the values of pic width in luma samples and pic height in luma samples, respectively, of the current picture, and RprConstraintsActive[slice_collocated_from_10_flag ? O:l][slice_collocated_ref_idx] shall be equal to 0.

[0067] Values of RprConstraintsActive[i][j] is derived in the section 8.3.2 in the VVC specification. The derivation of values of RprConstraints Active [i][j] is described below. Decoding Process for Reference Picture Lists Construction

[0068] The decoding process for reference picture lists construction is invoked at the beginning of the decoding process for each slice of a non-IDR picture.

[0069] Reference pictures are addressed through reference indices. A reference index is an index into a reference picture list. When decoding an I slice, no reference picture list is used in decoding of the slice data. When decoding a P slice, only reference picture list 0 (i.e., RefPicListf 0 ]), is used in decoding of the slice data. When decoding a B slice, both reference picture list 0 and reference picture list 1 (i.e., RefPicListf 1 ]) are used in decoding of the slice data.

[0070] At the beginning of the decoding process for each slice of a non-IDR picture, the reference picture lists RefPicListf 0 ] and RefPicListf 1 ] are derived. The reference picture lists are used in marking of reference pictures as specified in video coding standards or in decoding of the slice data.

[0071] For an I slice of a non-IDR picture that it is not the first slice of the picture, RefPicListf 0 ] and RefPicListf 1 ] may be derived for bitstream conformance checking purpose, but their derivation is not necessary for decoding of the current picture or pictures following the current picture in decoding order. For a P slice that it is not the first slice of a picture, RefPicListf 1 ] may be derived for bitstream conformance checking purpose, but its derivation is not necessary for decoding of the current picture or pictures following the current picture in decoding order.

[0072] The reference picture lists RefPicList[ 0 ] and RefPicList[ 1 ], the reference picture scaling ratios RefPicScale[ i ][ j ][ 0 ] and RefPicScale[ i ][ j ][ 1 ], and the reference picture scaled flags RprConstraintsActive[ 0 ][ j ] and RprConstraintsActive[ 1 ][ j ] are derived as follows: for( i = 0; i < 2; i++ ) { for(j = 0, k = 0, pocBase = PicOrderCntVal; j < num ref entries [ i ][ Rplsldx[ i ] ]; j++) { if( !inter layer ref_pic flag[ i ][ Rplsldx[ i ] ][ j ] ) { if( st ref_pic flag[ i ][ Rplsldx[ i ] ][ j ] ) {

RefPicPocList[ i ] [ j ] = pocBase - DeltaPocValSt[ i ] [ Rplsldx[ i ] ] [ j ] if( there is a reference picture picA in the DPB with the same null layer id as the current picture and PicOrderCntVal equal to RefPicPocList[ i ] [ j ] )

RefPicList[ i ][ j ] = picA else

RefPicList[ i ][ j ] = "no reference picture" (203) pocBase = RefPicPocList[ i ][ j ]

} else { if( !delta_poc msb cycle lt[ i ][ k ] ) { if( there is a reference picA in the DPB with the same null layer id as the current picture and

PicOrderCntVal & ( MaxPicOrderCntLsb - 1 ) equal to PocLsbLt[ i ] [ k ] ) RefPicList[ i ][ j ] = picA else

RefPicList[ i ][ j ] = "no reference picture"

RefPicLtPocList[ i ] [ j ] = PocLsbLt[ i ] [ k ]

} else { if( there is a reference picA in the DPB with the same null layer id as the current picture and

PicOrderCntVal equal to FullPocLt[ i ][ k ] ) RefPicList[ i ][ j ] = picA else

RefPicList[ i ][ j ] = "no reference picture" RefPicLtPocList[ i ] [ j ] = FullPocLt[ i ] [ k ]

} k++

}

} else { layerldx = DirectRefLayerIdx[ GeneralLayeridx[ null layer id ] ][ ilrp idx[ i ] [ Rplsldx ] [ j ] ] refPicLayerld = vps layer id [ layerldx ] if( there is a reference picture picA in the DPB with null layer id equal to refPicLayerld and the same PicOrderCntVal as the current picture )

RefPicList[ i ][ j ] = picA else

RefPicList[ i ][ j ] = "no reference picture"

} fRefWidth is set equal to PicOutputWidtliL of the reference picture RefPicList[ i ][ j ] fRefHeight is set equal to PicOutputFIeightL of the reference picture RefPicList[ i ][ j ] refPicWidth, refPicFIeight, refScalingWinLeftOffset, refScalingWinRightOffset, refS calingW inT opOff set, and refScalingWiiiBottomOffset, are set equal to the values of pic width in luma samples, pic height in luma samples, scaling win left offset, scaling win right offset, scaling win top offset, and scaling win bottom offset, respectively, of the reference picture RefPicList[ i ][j ]

RefPicScale[ i ][ j ][ 0 ]=( ( fRefWidth « 14 ) + ( PicOutputWidthL » 1 ) ) / PicOutputWidthL RefPicScale[ i ][ j ][ 1 ]=( ( fRefHeight « 14 ) + ( PicOutputHeightL » 1 ) ) / PicOutputHeightL RprConstraintsActive[ i ][j ] = ( pic width in luma samples != refPicWidth | | pic height in luma samples != refPicHeight 1 1 scaling win left offset != refScalingWinLeftOffset 1 1 scaling win _right offset != refScalingWinRightOffset 1 1 scaling win top offset != refScalingWinTopOffset | | scaling win bottom offset != refScalingWinBottomOffset )

}

}

[0073] scaling win left offset, scaling win right offset. scaling win top offset. and scaling win bottom offset specify the offsets that are applied to the picture size for scaling ratio calculation. When not present, the values of scaling_win_left_offset, scaling_win_right_offset, scaling_win_top_offset, and scaling_win_bottom_offset are inferred to be equal to pps conf win left offset, pps conf win right offset, pps conf win top offset, and pps conf win bottom offset, respectively.

[0074] The value of SubWidthC * ( scaling win left offset + scaling win right offset ) shall be less than pic width in luma samples, and the value of

SubHeightC * ( scaling_win_top_offset + scaling_win_bottom_offset ) shall be less than pic height in luma s ampl es .

[0075] The variables PicOutputWidthL and PicOutputHeightL are derived as follows: PicOutputWidthL = pic width in luma samples -

SubWidthC * ( scaling_win_right_offset + scaling_win_left_offset ) PicOutputHeightL = pic height in luma samples - (78)

SubWidthC * ( scaling_win_bottom_offset + scaling_win_top_offset ).

[0076] Let refPicOutputWidthL and refPicOutputHeightL be the PicOutputWidthL and PicOutputHeightL, respectively, of a reference picture of a current picture referring to this PPS. It is a requirement of bitstream conformance that all of the following conditions are satisfied:

- PicOutputWidthL * 2 shall be greater than or equal to refPicWidthlnLumaSamples.

- PicOutputHeightL * 2 shall be greater than or equal to refPicHeightlnLumaSamples.

- PicOutputWidthL shall be less than or equal to refPicWidthlnLumaSamples * 8.

- PicOutputHeightL shall be less than or equal to refPicHeightlnLumaSamples * 8.

- PicOutputWidthL * pic width max in luma samples shall be greater than or equal to refPicOutputWidthL * (pic width in luma samples - Max( 8, MinCbSizeY )). - PicOutputHeightL * pic height max in luma samples shall be greater than or equal to refPicOutputHeightL * (pic height in luma samples - Max( 8, MinCbSizeY )).

[0077] In current VVC, mvd_ll_zero_flag is signaled in the PH without any conditional constraint. However, the feature controlled by the flag mvd_ll_zero_flag is only applicable when the slice is a bi-predictive slice (B-slice). Therefore, the flag signaling is redundant when the slice associated with the picture header is not a B-slice.

[0078] In another example, ph disable bdof flag and ph disable dmvr flag are signaled in the PH only when the corresponding enabling flags (sps_bdof_pic_present_flag, sps_dmvr_pic_present_flag) signaled in sequence parameter set (SPS) are true, respectively. As shown in Table 2 below, however, the features controlled by the flags ph disable bdof flag and ph_disable_dmvr_flag are only applicable when the slice is a bi- predictive slice (B-slice). Therefore, the signaling of these two flags is redundant or useless when the slices associated with the picture header is not a B-slice.

Table 2

[0079] One more example can also be seen on the syntax elements ph_collocated_from_10_flag to indicate the collocatd picture is from listO or listl. And another exmaple can be seen on the syntax pred_weight_table( ) which are the syntax elements related to the weighting tabled for the bi-predictive preidction, as shown below.

current VVC, because the resolution of the collocated picture selected for TMVP derivation shall be the same as the resolution of the current picture, there is a bitstream conformance constraint to check the value of ph temporal mvp enabled flag as illustrated below. [0081] When no reference picture in the DPB has the same spatial resolution as the current picture, the value of ph temporal mvp enabled flag shall be equal to 0.

However, in current VVC, not only the resolution of the collocated picture will affect the enabling of TMVP, but also the offsets that are applied to the picture size for scaling ratio calculation affect the enabling of TMVP. In current VVC, however, the offsets are not considered in the bitstream conformance of ph_temporal_mvp_enabled_flag.

[0082] Moreover, there is a requirement of bitstream conformance that the picture referred to by slice collocated ref idx shall be the same for all slices of a coded picture. However, when a coded picture has multiple slices and there is no common reference picture existing among all these slices, this bitstream conformance has no chance to be met. And in such case, ph temporal mvp enabled flag should be constrained to be 0.

[0083] Several methods are proposed to address the issues described above. The proposed methods could be applied independently or combinedly.

[0084] Since the features controlled by the flags mvd_ll_zero_flag, ph disable bdof flag and ph_disable_dmvr_flag are only applicable when the slice is a bi-predictive slice (B- slice), according to a method of the disclosure, it is proposed to signal these flags only when the associated slices are B-slices. It is noted that when the reference picture lists are signaled in PH (e.g. rpl_info_in_ph_flag=l), it means all the slices of the coded picture use the same reference pictures signaled in PH. Therefore, when the reference picture lists are signaled in PH and the signaled reference picture lists indicate that the current picture is not bi- predictive, the flags mvd ll zero flag, ph disable bdof flag and ph disable dmvr flag need not to be signaled.

[0085] In some examples, some conditions are added to those syntaxes set in PH to prevent redundant signaling or undefined decoding behavior due to improper values sent for some of the syntaxes in the picture header. Some examples are illustrated below, wherein variables num_ref_entries[i][ Rplsldxf i ]] represent the number of reference pictures in the list i.

[0086] In some examples, the condition may be shown as below:

If (rpl info injh flag && num_ref_entries[ 0 ][ Rplsldxf 0 ] ] > 1 && num_ref_entries[ 1 ][ Rpl sldx | 1 ] ] > 1 ) mvd l l zero flag

[0087] In some examples, the condition may be shown as below:

If (!rpl_info_in_ph_flag || (rpl_info_in_ph_flag && num_ref_entries[ 0 ][ Rplsldxf 0 ] ] > 1 && num_ref_entries[ 1 ][ Rpl sldx | 1 ] ] > 1 )) mvclj 1 zero flag

[0088] In some examples, the condition may be shown as below:

If (!rpl_info_in_ph_flag || (rpl_info_in_ph_flag && num_ref_entries[ 0 ][ Rplsldx[ 0 ] ] > 0 && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 0 ) mvd l l zero flag

[0089] Alternatively, the conditions can be written in a more compact form which gives the same results. Because a bi-predictive slice (B-slice) or bi-predictive picture must have at least one listl reference picture, it can only check whether current slice/picture has listl reference picture. An example of the alternative condition checking is illustrated below:

If (!rpl_info_in_ph_flag || (rpl_info_in_ph_flag && num_ref_entries[ 1 ][ Rplsldxf 1 ] ] > 0 )) mvd l l zero flag

[0090] The semantics of mvd ll zero flag is also modified to handle the case when it is not signaled.

[0091] mvd_ll_zero_flag equal to 1 indicates that the mvd_coding( xO, yO, 1 ) syntax structure is not parsed and MvdLl[ xO ][ yO ][ compldx ] and

MvdCpLlf xO ][ yO ][ cpldx ][ compldx ] are set equal to 0 for compldx = 0..1 and cpldx = 0..2. mvd ll zero flag equal to 0 indicates that the mvd_coding( xO, yO, 1 ) syntax structure is parsed. When not present, the value of mvd_ll_zero_flag is inferred to be 0.

[0092] Several examples of conditionally signalling the syntax element ph disable dmvr flag are illustrated below:

If (sps_dmvr_pic_present_flag && rpl_info_in_ph_flag && num_ref_entries[ 0 ][ Rpl sldx | 0 ] ] > 1 && num_ref_entries[ 1 ][ Rplsldxf 1 ] ] > 1 ) ph disable dmvr flag or If (sps_dmvr_pic_present_flag && (!rpl_info_in_ph_flag || (rpl_info_in_ph_flag && num_ref_entries[ 0 ][ Rpl sldx | 0 ] ] > 1 && num_ref_entries[ 1 ][ Rplsldxf 1 ] ] > 1)) ) ph disable dmvr flag or If (sps_dmvr_pic_present_flag && (!rpl_info_in_ph_flag || (rpl_info_in_ph_flag && num_ref_entries[ 0 ][ Rpl sldx | 0 ] ] > 0 && num_ref_entries[ 1 ][ Rplsldxf 1 ] ] > 0)) ) ph disable dmvr flag

[0093] Another example of the alternative condition checking is illustrated below:

If (sps_dmvr_pic_present_flag && (!rpl_info_in_ph_flag || (rpl_info_in_ph_flag && num_ref_entries[ 1 ][ Rpl sldx | 1 ] ] > 0)) ) ph disable dmvr flag

[0094] The semantics of ph disable dmvr flag is also modified to handle the case when it is not signaled.

[0095] ph_disable_dmvr_flag equal to 1 specifies that decoder motion vector refinement based inter bi-prediction is disabled in the slices associated with the PH. ph disable dmvr flag equal to 0 specifies that decoder motion vector refinement based inter bi-prediction may or may not be enabled in the slices associated with the PH.

[0096] When ph disable dmvr flag is not present, the following applies:

- If sps dmvr enabled flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 0, the value of ph disable dmvr flag is inferred to be equal to 0.

- Else if sps dmvr enabled flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 1, the value of ph disable dmvr flag is inferred to be equal to 1.

- Otherwise (sps dmvr enabled flag is equal to 0), the value of ph disable dmvr flag is inferred to be equal to 1.

[0097] Another example to derive the value of ph disable dmvr flag when it is not presented is illustrated below: if all the conditions are considered for the derivation of the value of ph disable dmvr flag when it is either explicitly signalled or implicitly derived:

- If sps dmvr enabled flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 0, the value of ph disable dmvr flag is inferred to be equal to 0.

- Else if sps_dmvr_enabled_flag is equal to 0 and sps_dmvr_pic_present_flag is equal to 0, the value of ph disable dmvr flag is inferred to be equal to 1.

- Else if sps dmvr enabled flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 0, the value of ph disable dmvr flag is inferred to be equal to X. (X is explicitly signalled)

- Else if sps dmvr enabled flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldxf 1 ] ] > 0, the value of ph_disable_dmvr_flag is inferred to be equal to X. (X is explicitly signalled)

- Else (sps dmvr enabled flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldxf 1 ] ] ==0), the value of ph disable dmvr flag is inferred to be equal to 1. [0098] Since the syntax element ph disable dmvr flag is explicitly signalled under the third and the fourth conditions, they can be removed from the derivation of ph disable dmvr flag when ph disable dmvr flag is not present.

[0099] When ph disable dmvr flag is not present, the following applies:

- If sps dmvr enabled flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 0, the value of ph disable dmvr flag is inferred to be equal to 0.

- Else if sps_dmvr_enabled_flag is equal to 0 and sps_dmvr_pic_present_flag is equal to 0, the value of ph disable dmvr flag is inferred to be equal to 1.

- Else (sps dmvr enabled flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldxf 1 ] ] =0), the value of ph disable dmvr flag is inferred to be equal to 1.

[0100] The conditions can be editorially simplified as below: when ph_disable_ dmvr flag is not present, the following applies:

- If sps dmvr enabled flag is equal to 1 and sps_dmvr_pic_present_flag is equal to 0, the value of ph disable dmvr flag is inferred to be equal to 0.

- Otherwise (sps_dmvr_enabled_flag is equal to 0 or sps_dmvr_pic_present_flag is equal to 1), the value of ph disable dmvr flag is inferred to be equal to 1.

[0101] Another example to derive the value of ph disable dmvr flag when it is not presented is illustrated below:

When ph_disable_dmvr_flag is not present, the following applies:

- If sps_ dmvr_pic_present_flag is equal to 0, the value of ph disable dmvr flag is inferred to be equal to 1- sps dmvr enabled flag.

- Else if sps_dmvr_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 0, the value of ph disable dmvr flag is inferred to be equal to 1- sps_ dmvr enabled flag.

- Else if sps_dmvr_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldxf 1 ] ] > 0, the value of ph disable dmvr flag is inferred to be equal to 1- sps dmvr enabled flag.

- Else (sps_dmvr_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldxf 1 ] ] =0), the value of ph disable dmvr flag is inferred to be equal to 1. [0102] In some examples, since the syntax element ph disable dmvr flag is explicitly signalled under the second and the third conditions above, they can be removed from the derivation of ph disable dmvr flag when it is not present.

[0103] In some examples, when ph disable dmvr flag is not present, the following applies: if sps_dmvr_pic_present_flag is equal to 0, the value of ph_disable_dmvr_flag is inferred to be equal to 1- sps_ dmvr enabled flag; otherwise, the value of ph_disable_ dmvr flag is inferred to be equal to 1.

[0104] Several examples of conditionally signalling the syntax element ph disable bdof flag are illustrated below:

If (sps_bdof_pic_present_flag && rpl_info_in_ph_flag && num_ref_entries[ 0 ][ Rpl sldx | 0 ] ] > 1 && num_ref_entries[ 1 ][ Rplsldxf 1 ] ] > 1 ) ph disable bdof flag

Or If (sps_bdof_pic_present_flag && (!rpl_info_in_ph_flag || (rpl_info_in_ph_flag && num_ref_entries[ 0 ][ Rpl sldx | 0 ] ] > 1 && num_ref_entries[ 1 ][ Rpl sldx [ 1 ] ] > 1)) ) ph disable bdof flag

[0105] In some examples, an example of the alternative condition checking is illustrated below:

If (sps_bdof_pic_present_flag && (!rpl_info_in_ph_flag || (rpl_info_in_ph_flag && num_ref_entries[ 1 ][ Rpl sldx | 1 ] ] > 0)) ) ph disable bdof flag

[0106] The semantics of ph disable bdof flag is also modified to handle the case when it is not signaled.

[0107] ph disable bdof flag equal to 1 specifies that bi-directional optical flow inter prediction based inter bi-prediction is disabled in the slices associated with the PH. ph disable bdof flag equal to 0 specifies that bi-directional optical flow inter prediction based inter bi-prediction may or may not be enabled in the slices associated with the PH. [0108] When ph disable bdof flag is not present, the following applies:

- If sps bdof enabled flag is equal to 1 and sps_bdof_pic_present_flag is equal to 0, the value of ph disable bdof flag is inferred to be equal to 0.

- Else if sps bdof enabled flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1, the value of ph disable dmvr flag is inferred to be equal to 1.

- Otherwise (sps bdof enabled flag is equal to 0, the value of ph disable bdof flag is inferred to be equal to 1. [0109] An alternative way to derive the value of ph disable bdof flag when it is not presented is illustrated below:

If all the conditions are considered for the derivation of the value of ph disable bdof flag when it is either explicitly signalled or implicitly derived:

- If sps bdof enabled flag is equal to 1 and sps_bdof_pic_present_flag is equal to 0, the value of ph disable bdof flag is inferred to be equal to 0.

- Else if sps_bdof_enabled_flag is equal to 0 and sps_bdof_pic_present_flag is equal to 0, the value of ph disable bdof flag is inferred to be equal to 1.

- Else if sps bdof enabled flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 0, the value of ph disable bdof flag is inferred to be equal to X. (X is explicitly signalled)

- Else if sps bdof enabled flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 0, the value of ph_disable_bdof_flag is inferred to be equal to X. (X is explicitly signalled)

- Else (sps bdof enabled flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] ==0), the value of ph disable bdof flag is inferred to be equal to 1.

[0110] Since the syntax element ph disable bdof flag is explicitly signalled under the third and the fourth conditions, they can be removed from the derivation of ph disable bdof flag when ph disable bdof flag is not present:

[0111] When ph disable bdof flag is not present, the following applies:

- If sps bdof enabled flag is equal to 1 and sps_bdof_pic_present_flag is equal to 0, the value of ph disable bdof flag is inferred to be equal to 0.

- Else if sps_bdof_enabled_flag is equal to 0 and sps_bdof_pic_present_flag is equal to 0, the value of ph disable bdof flag is inferred to be equal to 1.

- Else (sps bdof enabled flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldxf 1 ] ] =0), the value of ph disable bdof flag is inferred to be equal to 1.

[0112] The conditions can be editorially simplified as below:

When ph_disable_bdof_flag is not present, the following applies:

- If sps bdof enabled flag is equal to 1 and sps_bdof_pic_present_flag is equal to 0, the value of ph disable bdof flag is inferred to be equal to 0. - Otherwise (sps_bdof_enabled_flag is equal to 0 or sps_bdof_pic_present_flag is equal to 1), the value of ph disable bdof flag is inferred to be equal to 1.

[0113] Another alternative way to derive the value of ph disable bdof flag when it is not presented is illustrated below: when ph disable bdof flag is not present, the following applies:

- If sps_bdof_pic_present_flag is equal to 0, the value of ph disable bdof flag is inferred to be equal to 1- sps bdof enabled flag.

- Else if sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 0, the value of ph disable bdof flag is inferred to be equal to 1- sps bdof enabled flag.

- Else if sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 0, the value of ph disable bdof flag is inferred to be equal to 1- sps bdof enabled flag.

- Else (sps_bdof_pic_present_flag is equal to 1 and rpl_info_in_ph_flag is equal to 1 and num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] ==0), the value of ph disable bdof flag is inferred to be equal to 1.

[0114] In some examples, since the syntax element ph disable bdof flag is explicitly signalled under the second and the third conditions, they can be removed from the derivation of ph disable bdof flag when it is not present.

[0115] When ph disable bdof flag is not present, the following applies:

- If sps_bdof_pic_present_flag is equal to 0, the value of ph disable bdof flag is inferred to be equal to 1- sps bdof enabled flag..

- Otherwise, the value of ph disable bdof flag is inferred to be equal to 1.

[0116] Moreover, the signalling conditions for syntax elements ph_collocated_from_10_flag and weight_table( ) are modified because the two types of syntax elements are only applicable when the associated slices are B-sbces. Examples of the modified syntax elements signaling are illustrated below. or

[0117] The semantics of ph collocated from lO flag is also modified to handle the case when it is not signaled. [0118] ph_collocated_from_10_flag equal to 1 specifies that the collocated picture used for temporal motion vector prediction is derived from reference picture list 0. ph collocated from lO flag equal to 0 specifies that the collocated picture used for temporal motion vector prediction is derived from reference picture list 1.

[0119] When ph collocated from lO flag is not present, the following applies:

- If num_ref_entries[ 0 ][ Rplsldxf 0 ] ] is larger than 1, the value of ph collocated from lO flag is inferred to be 1.

- Otherwise (num_ref_entries[ 1 ][ Rplsldxf 1 ] ] is larger than 1 ), the value of ph_collocated_from_10_flag is inferred to be 0.

if( pps_weighted_bipred_flag && wp_info_in_ph_flag && (!rpl_info_in_ph_flag || (rpl_info_in_ph_flag && num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] > 0))) num ll weights

[0121] The semantics of the syntax elements in pred_weight_table( ) are also modified to handle the case when they are not signaled.

[0122] num ll weights specifies the number of weights signalled for entries in reference picture list 1 when pps weighted bipred flag and wp_info_in_ph_flag are both equal to 1. The value of num_ll_weights shall be in the range of 0 to Min( 15, num_ref_entries[ 1 ][ Rpl sldx | 1 ] ] ), inclusive.

[0123] The variable NumWeightsLl is derived as follows: if( !pps_weighted_bipred_flag)

NumWeightsLl = 0 else if (wp_info_in_ph_flag && rpl_info_in_ph_flag && (num_ref_entries[ 0 ][ Rpl sldx I 0 ] ] ==0 II num_ref_entries[ 1 ][ Rpl sldx [ 1 ] ] >=0))

NumWeightsLl = 0 else if( wp_info_in_ph_flag )

NumWeightsLl = num ll weights else

NumWeightsLl = NumRefldxActivef 1 ] [0124] In the semantics of the syntax elements in pred_weight_table( ), an alternative way to derive the value of num_ll_weights when it is not presented is illustrated below: num_ll_weights specifies the number of weights signalled for entries in reference picture list 1 when pps weighted bipred flag and wp_info_in_ph_flag are both equal to 1. The value of num_ll_weights shall be in the range of 0 to Min( 15, num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] ), inclusive. When not present, the value of num_ll_weights is inferred to be 0.

[0125] The variable NumWeightsLl is derived as follows: if( !pps_weighted_bipred_flag)

NumWeightsLl = 0 else if( wp_info_in_ph_flag )

NumWeightsLl = num ll weights else

NumWeightsLl = NumRefldxActivef 1 ]

[0126] In the semantics of the syntax elements in pred_weight_table( ), another alternative way to derive the value of num_ll_weights when it is not presented is illustrated below: if( !pps_weighted_bipred_flag | | ( wp_info_in_ph_flag && num_ref_entries[ 1 ] [ Rplsldxf 1 ] ] = = 0 ) )

NumWeightsLl = 0 else if( wp_info_in_ph_flag )

NumWeightsLl = num ll weights else

NumWeightsLl = NumRefldxActivef 1 ]

[0127] Conceptually, it is proposed to add signaling condition to check whether the current picture has reference pictures from both listO and listl reference picure lists for any syntax elements which is only applicable in B slices to avoid signaling redundant bits. The checking condition is not limited to the above mentioned method to check the size of both reference picture lists (e.g. list 0/listl reference picture lists) and the checing condition may be any other method to indicate whether current picture has reference pictures from both listO and listl reference picture lists. For example, a flag can be signaled to indicate whether current picture has both listO and litsl reference pictures.

[0128] When the syntax elements are not signaled and the reference picture list information is signaled in the picture header (PH), the values of the syntax elements are derived using the information whether current picture has both listO and listl reference pictures or it has only listO or listl reference pictures. In one example, when ph collocated from lO flag is not signaled, its value is inferred to be the only reference picture that current picture has. In another example, when sps bdof enabled flag is equal to 1 and sps_bdof_pic_present_flag is equal to 1 but ph disable bdof flag is not signalled, it implies that either num_ref_entries[ 0 ][ Rplsldx[ 0 ] ] is equal to 0 or num_ref_entries[ 1 ][ Rplsldx[ 1 ] ] is equal to 0 according the proposed signalling condition on ph disable bdof flag. Therefore, under this condition, ph disable bdof flag is not signalled and is inferred as 1. In current VVC, not only the resolution of the collocated picture may affect the enabling of TMVP but also the offsets applied to the picture size for scaling ratio calculation may affect the enabling of TMVP. In current VVC, however, the offsets are not considered in the bitstream conformance of ph temporal mvp enabled flag. In the second embodiment, it is proposed to add a bitstream conformance constraint to the current VVC requiring that the value of ph temporal mvp enabled flag shall be dependent on the offsets that are applied to the picture size for scaling ratio calculation, as illustrated below.

[0129] When no reference picture in the DPB has the same spatial resolution and the same offsets that are applied to the picture size for scaling ratio calculation as the current picture, the value of ph temporal mvp enabled flag shall be equal to 0.

[0130] The above sentences can also be written in another way as below: when no reference picture in the DPB has the associated variable value RprConstraintsActivel i ][ j ] equal to 0, the value of ph temporal mvp enabled flag shall be equal to 0.

[0131] In current VVC, there is a requirement of bitstream conformance that the picture referred to by slice collocated ref idx shall be the same for all slices of a coded picture. However, when the coded picture has multiple slices and there is no common reference picture existing among all these slices, this bitstream conformance has no chance to be met.

In the third embodiment of the disclosure, the requirement of bitstream conformance on ph temporal mvp enabled flag is modified to consider whether there is a common reference picture existing among all the slices in the current picture. Based on the embodiment, several exemplary modifications to the VVC specification are illustrated below.

[0132] ph temporal mvp enabled flag specifies whether temporal motion vector predictors can be used for inter prediction for slices associated with the PH. If ph temporal mvp enabled flag is equal to 0, the syntax elements of the slices associated with the PH shall be constrained such that no temporal motion vector predictor is used in decoding of the slices. Otherwise (ph temporal mvp enabled flag is equal to 1), temporal motion vector predictors may be used in decoding of the slices associated with the PH. When not present, the value of ph temporal mvp enabled flag is inferred to be equal to 0. When no reference picture in the DPB has the same spatial resolution as the current picture, the value of ph temporal mvp enabled flag shall be equal to 0. When no common reference picture exists in all the slices associated with the PH, the value of ph temporal mvp enabled flag shall be equal to 0.

[0133] ph temporal mvp enabled flag specifies whether temporal motion vector predictors can be used for inter prediction for slices associated with the PH. If ph_temporal_mvp_enabled_flag is equal to 0, the syntax elements of the slices associated with the PH shall be constrained such that no temporal motion vector predictor is used in decoding of the slices. Otherwise (ph temporal mvp enabled flag is equal to 1), temporal motion vector predictors may be used in decoding of the slices associated with the PH. When not present, the value of ph temporal mvp enabled flag is inferred to be equal to 0. When no reference picture in the DPB has the same spatial resolution as the current picture, the value of ph temporal mvp enabled flag shall be equal to 0. When no common reference picture exists in all the inter slices associated with the PH, the value of ph temporal mvp enabled flag shall be equal to 0.

[0134] ph temporal mvp enabled flag specifies whether temporal motion vector predictors can be used for inter prediction for slices associated with the PH. If ph_temporal_mvp_enabled_flag is equal to 0, the syntax elements of the slices associated with the PH shall be constrained such that no temporal motion vector predictor is used in decoding of the slices. Otherwise (ph temporal mvp enabled flag is equal to 1), temporal motion vector predictors may be used in decoding of the slices associated with the PH. When not present, the value of ph temporal mvp enabled flag is inferred to be equal to 0. When no reference picture in the DPB has the same spatial resolution as the current picture, the value of ph temporal mvp enabled flag shall be equal to 0. When no common reference picture exists in all the non-intra slices associated with the PH, the value of ph temporal mvp enabled flag shall be equal to 0.

[0135] In one example, the bitstream conformance on slice collocated ref idx is simplified as below: [0136] It is a requirement of bitstream conformance that the values of pic width in luma samples and pic height in luma samples of the reference picture referred to by slice collocated ref idx shall be equal to the values of pic width in luma samples and pic height in luma samples, respectively, of the current picture, and RprConstraintsActive[ slice_collocated_from_10_flag ? 0 :

1 ][ slice collocated ref idx ] shall be equal to 0.

[0137] The above methods may be implemented using an apparatus that includes one or more circuitries, which include application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, micro-controllers, microprocessors, or other electronic components. The apparatus may use the circuitries in combination with the other hardware or software components for performing the above described methods. Each module, sub-module, unit, or sub-unit disclosed above may be implemented at least partially using the one or more circuitries.

[0138] In current VVC spec, we have two bitstream conformance on the limitation of the resolution of the collocated picture. One is posed on the ph_temporal_mvp_enabled_flag and the other one is posed on the bitstream conformance on slice collocated ref idx. However, it is redundant having the two bitstreams confromance in the VVC spec in terms of funcationality because they both prohibit using a collocated picture which has different resolution and/or different scaling offsets from the current picture. To reduce the burdan of the encoder to check the bitstream confromacne, in the fifth embodiment, it is proposed to apply only the bitstream confromace slice collocated ref idx. An example of the revised specification of VVC is illustrated below. The changed parts are highlighted.

[0139] In one example, it is proposed to apply only the bitstream conformance ph_temporal_mvp_enabled_flag. An example of the revised specification of VVC is illustrated below.

[0140] FIG. 5 is a block diagram illustrating an exemplary apparatus for video coding in accordance with some implementations of the present disclosure. The apparatus 500 may be a terminal, such as a mobile phone, a tablet computer, a digital broadcast terminal, a tablet device, or a personal digital assistant.

[0141] As shown in FIG. 5, the apparatus 500 may include one or more of the following components: a processing component 502, a memory 504, a power supply component 506, a multimedia component 508, an audio component 510, an input/output (I/O) interface 512, a sensor component 514, and a communication component 516. [0142] The processing component 502 usually controls overall operations of the apparatus 500, such as operations relating to display, a telephone call, data communication, a camera operation and a recording operation. The processing component 502 may include one or more processors 520 for executing instructions to complete all or a part of steps of the above method. Further, the processing component 502 may include one or more modules to facilitate interaction between the processing component 502 and other components. For example, the processing component 502 may include a multimedia module to facilitate the interaction between the multimedia component 508 and the processing component 502.

[0143] The memory 504 is configured to store different types of data to support operations of the apparatus 500. Examples of such data include instructions, contact data, phonebook data, messages, pictures, videos, and so on for any application or method that operates on the apparatus 500. The memory 504 may be implemented by any type of volatile or non-volatile storage devices or a combination thereof, and the memory 504 may be a Static Random Access Memory (SRAM), an Electrically Erasable Programmable Read-Only Memory (EEPROM), an Erasable Programmable Read-Only Memory (EPROM), a Programmable Read-Only Memory (PROM), a Read-Only Memory (ROM), a magnetic memory, a flash memory, a magnetic disk or a compact disk.

[0144] The power supply component 506 supplies power for different components of the apparatus 500. The power supply component 506 may include a power supply management system, one or more power supplies, and other components associated with generating, managing and distributing power for the apparatus 500.

[0145] The multimedia component 508 includes a screen providing an output interface between the apparatus 500 and a user. In some examples, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen receiving an input signal from a user. The touch panel may include one or more touch sensors for sensing a touch, a slide and a gesture on the touch panel. The touch sensor may not only sense a boundary of a touching or sliding actions, but also detect duration and pressure related to the touching or sliding operation. In some examples, the multimedia component 508 may include a front camera and/or a rear camera. When the apparatus 500 is in an operation mode, such as a shooting mode or a video mode, the front camera and/or the rear camera may receive external multimedia data.

[0146] The audio component 510 is configured to output and/or input an audio signal. For example, the audio component 510 includes a microphone (MIC). When the apparatus 500 is in an operating mode, such as a call mode, a recording mode and a voice recognition mode, the microphone is configured to receive an external audio signal. The received audio signal may be further stored in the memory 504 or sent via the communication component 516. In some examples, the audio component 510 further includes a speaker for outputting an audio signal.

[0147] The I/O interface 512 provides an interface between the processing component 502 and a peripheral interface module. The above peripheral interface module may be a keyboard, a click wheel, a button, or the like. These buttons may include but not limited to, a home button, a volume button, a start button and a lock button.

[0148] The sensor component 514 includes one or more sensors for providing a state assessment in different aspects for the apparatus 500. For example, the sensor component 514 may detect an on/off state of the apparatus 500 and relative locations of components. For example, the components are a display and a keypad of the apparatus 500. The sensor component 514 may also detect a position change of the apparatus 500 or a component of the apparatus 500, presence or absence of a contact of a user on the apparatus 500, an orientation or acceleration/deceleration of the apparatus 500, and a temperature change of apparatus 500. The sensor component 514 may include a proximity sensor configured to detect presence of a nearby object without any physical touch. The sensor component 514 may further include an optical sensor, such as a CMOS or CCD image sensor used in an imaging application. In some examples, the sensor component 514 may further include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0149] The communication component 516 is configured to facilitate wired or wireless communication between the apparatus 500 and other devices. The apparatus 500 may access a wireless network based on a communication standard, such as WiFi, 4G, or a combination thereof. In an example, the communication component 516 receives a broadcast signal or broadcast related information from an external broadcast management system via a broadcast channel. In an example, the communication component 516 may further include a Near Field Communication (NFC) module for promoting short-range communication. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, Ultra-Wide Band (UWB) technology, Bluetooth (BT) technology and other technology.

[0150] In an example, the apparatus 500 may be implemented by one or more of Application Specific Integrated Circuits (ASIC), Digital Signal Processors (DSP), Digital Signal Processing Devices (DSPD), Programmable Logic Devices (PLD), Field Programmable Gate Arrays (FPGA), controllers, microcontrollers, microprocessors or other electronic elements to perform the above method.

[0151] A non-transitory computer readable storage medium may be, for example, a Hard Disk Drive (HDD), a Solid-State Drive (SSD), Flash memory, a Hybrid Drive or Solid-State Hybrid Drive (SSHD), a Read-Only Memory (ROM), a Compact Disc Read-Only Memory (CD-ROM), a magnetic tape, a floppy disk and etc.

[0152] FIG. 6 is a flowchart illustrating an exemplary process of video coding in accordance with some implementations of the present disclosure.

[0153] In step 602, the processor 520 determines whether a disable flag is present in a PH associated with a picture.

[0154] In some examples, the disable flag specifies whether a coding tool is disabled in one or more slices associated with the PH.

[0155] In step 604, the processor 520 infers value of the disable flag according to one or more enable flags signaled in SPS of the picture in response to determining that the disable flag is not present in the PH.

[0156] In some examples, the processor 520 disables the coding tool in decoding the one or more slices in response to determining that the value of the disable flag equals to 1 and enables the coding tool in decoding the one or more slices in response to determining that the value of the disable flag equals to 0.

[0157] In some examples, the coding tool includes at least one of DMVR based inter bi prediction and BDOF based inter bi-prediction.

[0158] In some examples, the processor 520 skips parsing the disable flag in response to determining that one or more reference picture lists indicate that one or more slices associated with the picture are not bi-predictive.

[0159] In some examples, the disable flag specifies whether the DMVR based inter bi prediction is disabled in the one or more slices associated with the PH, the processor 520 disables the coding tool in decoding the one or more slices by disabling the DMVR based inter bi-prediction in decoding the one or more slices, and the processor 520 enables the coding tool in decoding the one or more slices by enabling the DMVR based inter bi prediction in decoding the one or more slices.

[0160] In some examples, the processor 520 infers the value of the disable flag according to the one or more enable flags signaled in the SPS of the picture in response to determning that parsing of the diable flag is skipped by inferring the value of the disalbe flag to be 0 in response to determining that a first enable flag in the SPS equals to 1 and a second enable flag in the SPS equals to 0.

[0161] In some exmaples, the first enable flag in the SPS specifies whether the DMVR based inter bi-prediction is enabled, the first enable flag equaling to 1 specifies that the DMVR based inter bi-prediction is enabled, and the first enable flag equaling to 0 specifies that the DMVR based inter bi-prediction is disabled.

[0162] In some examples, the second enable flag in the SPS specifies whether the disable flag is present in the PH referring to the SPS, the second enable flag equaling to 0 specifies that the disable flag is not present in the PH referring to the SPS, and the second enable flag equaling to 1 specifies that the disable flag is present in the PH referring to the SPS.

[0163] In some examples, the processor 520 infers the value of the disable flag according to the one or more enable flags signaled in the SPS of the picture in response to determning that parsing of the diable flag is skipped by inferring the value of the disable flag to be 1 in response to determining that the first enable flag in the SPS equals to 1 and the second enable flag in the SPS equals to 1 and inferring the value of the disable flag to be 1 in response to determining that the first enable flag in the SPS equals to 0.

[0164] In some examples, the processor 520 infers the value of the disable flag according to the one or more enable flags signaled in the SPS of the picture in response to determning that parsing of the diable flag is skipped by inferring the disable flag to be 1 in response to determining that the first enable flag in the SPS equals to 0 and the second enable flag in the SPS equals to 0 and inferring the value of the disable flag to be 1 in response to determining that the first enable flag in the SPS equals to 1, the second enable flag in the SPS equals to 1, one or more reference picture lists are signaled in the PH, and a number of reference pictures in a second reference picture list equals to 0. The one or more refence picture lists include a first reference picture list and the second reference picture list.

[0165] In some examples, the processor 520 infers the value of the disable flag according to the one or more enable flags signaled in the SPS of the picture in response to determning that parsing of the diable flag is skipped by inferring the value of the disable flag to be 1 in response to determining that the first enable flag in the SPS equals to 0 and inferring the value of the disable flag to be 1 in response to determining that the second enable flag in the SPS equals to 1. [0166] In some examples, the processor 520 determines value of a first enable flag in the SPS as W, and the first enable flag in the SPS specifies whether the DMVR based inter bi prediction is enabled, the first enable flag equaling to 1 specifies that the DMVR based inter bi-prediction is enabled, and the first enable flag equaling to 0 specifies that the DMVR based inter bi-prediction is disabled. The processor 520 infers the value of the disable flag according to the one or more enable flags signaled in the SPS of the picture in response to determning that parsing of the diable flag is skipped by inferring the value of the disable flag to be 1-W in response to determining that a second enable flag in the SPS equals to 0. The second enable flag in the SPS specifies whether the disable flag is present in the PH referring to the SPS, the second enable flag equaling to 0 specifies that the disable flag is not present in the PH referring to the SPS, and the second enable flag equaling to 1 specifies that the disable flag is present in the PH referring to the SPS.

[0167] In some examples, the processor 520 infers the value of the disable flag according to the one or more enable flags signaled in the SPS of the picture in response to determning that parsing of the diable flag is skipped by inferring the value of the disable flag to be 1 in response to determining that the second enable flag in the SPS does not equal to 0.

[0168] In some examples, the processor 520 inferrs the value of the disable flag to be 1 in response to determining that the second enable flag in the SPS does not equal to 0 by inferring the value of the disable flag to be 1 in response to determining that the second enable flag in the SPS equals to 1, one or more reference picture lists are signaled in the PH, and a number of reference pictures in a second reference picture list equals to 0. The one or more reference picture lists includes a first reference picture list and the second reference picture list.

[0169] In some examples, the processor 520 infers the value of the disable flag according to the one or more enable flags in the SPS in response to determining that the disable flag is signaled in the PH.

[0170] In some examples, the processor 520 infers the value of the disable flag according to the one or more enable flags in the SPS in response to determining that the disable flag is signaled in the PH by: determining a value of a first enable flag in the SPS as W; inferring the value of the disable flag to be 1-W in response to determining that a second enable flag in the SPS equals to 1 and one or more reference picture lists are not signaled in the PH; inferring the value of the disable flag to be 1-W in response to determining that the second enable flag in the SPS equals to 1, the one or more reference picture lists are signaled in the PH, and a number of reference pictures in the reference picture list 1 is greater than 0.

[0171] In some examples, the processor 520 infers the value of the disable flag according to the one or more enable flags in the SPS in response to determining that the disable flag is signaled in the PH by: inferring the value of the disable flag to be a value of the disable flag explicitly signaled in the PH in response to determining that a first enable flag in the SPS equals to 1, a second enable flag in the SPS equals to 1, and one or more reference picture lists are not signaled in the PH; inferring the value of the disable flag to be the value of the disable flag explicitly signaled in the PH in response to determining that the first enable flag in the SPS equals to 1, the second enable flag in the SPS equals to 1, the one or more reference picture lists are signaled in the PH, and a number of reference pictures in the reference picture list 1 is greater than 0.

[0172] In some examples, the disable flag specifies whether the BDOF based inter bi prediction is disabled in the one or more slices associated with the PH. The processor 520 diables the coding tool in decoding the one or more slices by disabling the BDOF based inter bi-prediction in decoding the one or more slices and enables the coding tool in decoding the one or more slices by enabling the BDOF based inter bi-prediction in decoding the one or more slices.

[0173] In some examples, the processor 520 infers the value of the disable flag according to the one or more enable flags signaled in the SPS of the picture in response to determining that parsing of the disable flag is skipped by inferring the value of the diable flag to be 0 in response to determining that a third enable flag in the SPS equals to 1 and a fourth enable flag in the SPS equals to 0. The third enable flag in the SPS specifies whether the BDOF based inter bi-prediction is enabled, the third enable flag equaling to 1 specifies that the BDOF based inter bi-prediction is enabled, and the third enable flag equaling to 0 specifies that the BDOF based inter bi-prediction is disabled. The fourth enable flag in the SPS specifies whether the disable flag is present in the PH referring to the SPS, the fourth enable flag equaling to 0 specifies that the disable flag is not present in the PH referring to the SPS, and the fourth enable flag equaling to 1 specifies that the disable flag is present in the PH referring to the SPS.

[0174] In some examples, the processor 520 infers the value of the disable flag according to the one or more enable flags signaled in the SPS of the picture in response to determining that the parsing of the disable flag is skipped by inferring the value of the disable flag to be 1 in response to determining that the third enable flag in the SPS equals to 1 and the fourth enable flag in the SPS equals to 1 and inferring the value of the disable flag to be 1 in response to determining that the third enable flag in the SPS equals to 0.

[0175] In some examples, the processor 520 infers the value of the disable flag according to the one or more enable flags signaled in the SPS of the picture in response to determining that the parsing of the disable flag is skipped by inferring the disable flag to be 1 in response to determining that the third enable flag in the SPS equals to 0 and the fourth enable flag in the SPS equals to 0 and inferring the value of the disable flag to be 1 in response to determining that the third enable flag in the SPS equals to 1, the fourth enable flag in the SPS equals to 1, one or more reference picture lists are signaled in the PH, and a number of reference pictures in a second reference picture list equals to 0. The one or more reference picture lists include a first reference picture list and the second reference picture list.

[0176] In some examples, the processor 520 infers the value of the disable flag according to the one or more enable flags signaled in the SPS of the picture in response to determining that the parsing of the disable flag is skipped by inferring the value of the disable flag to be 1 in response to determining that the third enable flag in the SPS equals to 0 and inferring the value of the disable flag to be 1 in response to determining that the fourth enable flag in the SPS equals to 1.

[0177] In some examples, the processor 520 determines value of a third enable flag in the SPS as V and inferrs the value of the disable flag according to the one or more enable flags signaled in the SPS of the picture by inferring the value of the disable flag to be 1-V in response to determining that a fourth enable flag in the SPS equals to 0.

[0178] In some examples, the processor 520 infers the value of the disable flag according to the one or more enable flags signaled in the SPS of the picture in response to determining that the parsing of the disable flag is skipped by infers the value of the disable flag to be 1 in response to determining that the fourth enable flag in the SPS does not equal to 0.

[0179] In some examples, the processor 520 infers the value of the disable flag to be 1 in response to determining that the fourth enable flag in the SPS does not equal to 0 by inferring the value of the disable flag to be 1 in response to determining that the fourth enable flag in the SPS equals to 1, one or more reference picture lists are signaled in the PH, and a number of reference pictures in a second reference picture list equals to 0. The one or more reference picture lists include a first reference picture list and the second reference picture list. [0180] In some examples, the processor 520 determines a value of a third enable flag in the SPS as V and infers the value of the disable flag according to the one or more enable flags in the SPS in response to determining that the disable flag is signaled in the PH by: inferring the value of the disable flag to be 1-V in response to determining that a fourth enable flag in the SPS equals to 1 and one or more reference picture lists are not signaled in the PH; and infrring the value of the disable flag to be 1-V in response to determining that the fourth enable flag in the SPS equals to 1, the one or more reference picture lists are signaled in the PH, and a number of reference pictures in the reference picture list 1 is greater than 0.

[0181] In some examples, the processor 520 infers the value of the disable flag to be a value of the disable flag explicitly signalled in the PH in response to determining that a third enable flag in the SPS equals to 1, a fourth enable flag in the SPS equals to 1, and one or more reference picture lists are not signaled in the PH and infers the value of the disable flag to be the value of the disable flag explicitly signalled in the PH in response to determining that the third enable flag in the SPS equals to 1, the fourth enable flag in the SPS equals to 1, the one or more reference picture lists are signaled in the PH, and a number of reference pictures in the reference picture list 1 is greater than 0.

[0182] FIG. 7 is a flowchart illustrating an exemplary process of video coding in accordance with some implementations of the present disclosure.

[0183] In step 702, the processor 520 determines whether a flag is present in a PH associated with a picture.

[0184] In some examples, the flag specifies whether the picture used for TMVP is derived from a reference picture list from a plurality of reference picture lists associated with the picture.

[0185] In step 704, the processor 520 infers value of the flag according to a number of reference pictures in the reference picture list in response to determining that the flag is not present in the PH.

[0186] In some examples, the processor 520 skips parsing the flag in response to determining that the plurality of reference picture lists indicate that one or more slices associated with the picture are not bi-predictive.

[0187] In some examples, the plurality of reference picture lists include a first reference picture list and a second reference picture list. [0188] In some examples, the flag equaling to 1 specifies that the picture used for TMVP is derived from the first reference picture list, and the flag equaling to 0 specifies that the picture used for TMVP is derived from the second reference picture list.

[0189] In some examples, the processor 520 infers the value of the flag according to the number of reference pictures in the reference picture list in response to determining that parsing of the flag is skipped by inferring the value of the flag to be 1 in response to determining that the number of reference pictures in the first reference picture list is greater than 1 and inferring the value of the flag to be 0 in response to determining that the number of reference pictures in the second reference picture list is greater than 1.

[0190] FIG. 8 is a flowchart illustrating an exemplary process of video coding in accordance with some implementations of the present disclosure.

[0191] In step 802, the processor 520 determines whether a flag is present in a PH associated with a picture.

[0192] In some examples, the flag specifies a number of weights signaled in a reference picture list according to a first WP flag in PPS of the picture and a second WP flag in the PH of the picture and the flag is in a WP syntax associated with the picture.

[0193] In step 804, the processor 520 infers value of the flag according to a number of reference pictures in a reference picture list from a plurality of refence picture lists associated with the picture in response to determining that the flag is not present in the PH.

[0194] In some examples, the processor 520 skips parsing the flag in response to determining that the plurality of reference picture lists indicate that one or more slices associated with the picture are not bi-predictive.

[0195] In some examples, the plurality of refence picture lists include a first reference picture list and a second reference picture list, the flag specifies the number of weights signaled in the second reference picture list in response to determining that the first WP flag in the PPS equals to 1 and the second WP flag in the PH equals to 1.

[0196] In some examples, the processor 520 infers the value of the flag according to the number of reference pictures in the reference picture list associated with the picture in response to determining that parsing of the flag is skipped by inferring the value of the flag to be 0 in response to determining that the first WP flag in the PPS equals to 0, the second WP flag in the PH equals to 1, and the number of reference pictures in the second reference picture list equals to 0, inferring the value of the flag to be a value of the flag explicitly signaled in the PH in response to determining that the first WP flag in the PPS does not equal to 0 and the second WP flag in the PH equals to 1, and inferring the value of the flag to be a value of NumRefldxActivef 1 ] in response to determining that the first WP flag in the PPS does not equal to 0 and the second WP flag in the PH does not equal to 1.

[0197] In some examples, value of NumRefldxActivef i ] - 1 specifies a maximum reference index for a reference picture list i, where i equals to 0 or 1.

[0198] For example, value ofNumRefldxActivef 1 ] - 1 specifies a maximum reference index for the reference picture list 1, that is, the second reference picture list.

[0199] In some examples, the processor 520 determines the value of the flag in response to determining that the flag is present in the PH by determining the value of the flag as 0 in response to determining the first WP flag in the PPS equals to 0, determining the value of the flag to be a value of the flag explicitly signaled in the PH in response to determining the first WP flag in the PPS does not equal to 0 and the second WP flag in the PH equals to 1, and determining the value of the flag to be a value of NumRefldxActivef 1 ] in response to determining that the first WP flag in the PPS does not equal to 0 and the second WP flag in the PH does not equal to 1.

[0200] FIG. 9 is a flowchart illustrating an exemplary process of video coding in accordance with some implementations of the present disclosure.

[0201] In step 902, the processor 520 uses an enabled flag to specify whether one or more temporal motion vector predictors used for inter prediction for one or more slices associated with a PH of a picture.

[0202] In step 904, the processor 520 constrains value of the enabled flag according to a plurality of offsets applied to a size of the picture for scaling ratio calculation.

[0203] In some examples, the processor sets the enabled flag to 0 in response to determining that there is no common inference picture in one or more inter slices. The one or more slices include the one or more inter slices associated with the PH.

[0204] In some examples, the processor sets the enabled flag to 0 in response to determining that there is no common inference picture in one or more non-intra slices.

[0205] In some examples, there is provided an apparatus for video coding. The apparatus includes one or more processors 520; and a memory 504 configured to store instructions executable by the one or more processors; where the processor, upon execution of the instructions, is configured to perform a method as illustrated in FIG. 6.

[0206] In some examples, there is provided an apparatus for video coding. The apparatus includes one or more processors 520; and a memory 504 configured to store instructions executable by the one or more processors; where the processor, upon execution of the instructions, is configured to perform a method as illustrated in FIG. 7.

[0207] In some examples, there is provided an apparatus for video coding. The apparatus includes one or more processors 520; and a memory 504 configured to store instructions executable by the one or more processors; where the processor, upon execution of the instructions, is configured to perform a method as illustrated in FIG. 8.

[0208] In some examples, there is provided an apparatus for video coding. The apparatus includes one or more processors 520; and a memory 504 configured to store instructions executable by the one or more processors; where the processor, upon execution of the instructions, is configured to perform a method as illustrated in FIG. 9.

[0209] In some other examples, there is provided a non-transitory computer readable storage medium 504, having instructions stored therein. When the instructions are executed by one or more processors 520, the instructions cause the processor to perform a method as illustrated in FIG. 6.

[0210] In some other examples, there is provided a non-transitory computer readable storage medium 504, having instructions stored therein. When the instructions are executed by one or more processors 520, the instructions cause the processor to perform a method as illustrated in FIG. 7.

[0211] In some other examples, there is provided a non-transitory computer readable storage medium 504, having instructions stored therein. When the instructions are executed by one or more processors 520, the instructions cause the processor to perform a method as illustrated in FIG. 8.

[0212] In some other examples, there is provided a non-transitory computer readable storage medium 504, having instructions stored therein. When the instructions are executed by one or more processors 520, the instructions cause the processor to perform a method as illustrated in FIG. 9.

[0213] The description of the present disclosure has been presented for purposes of illustration, and is not intended to be exhaustive or limited to the present disclosure. Many modifications, variations, and alternative implementations will be apparent to those of ordinary skill in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings.

[0214] The examples were chosen and described in order to explain the principles of the disclosure, and to enable others skilled in the art to understand the disclosure for various implementations and to best utilize the underlying principles and various implementations with various modifications as are suited to the particular use contemplated. Therefore, it is to be understood that the scope of the disclosure is not to be limited to the specific examples of the implementations disclosed and that modifications and other implementations are intended to be included within the scope of the present disclosure.