Background

[0001] For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, lending to the fabrication of products with increased capacity. The drive for the ever-increasing capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. In particular, further improvements in the area of lithographic manufacturing technologies are always desirable.

Brief Description of the Drawings

[0002] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0003] FIG. 1 is a flow diagram of an example method of manufacturing a device by combining mask-based and maskless lithography, in accordance with various embodiments.

[0004] FIG. 2 is a cross-sectional side view of a device including a plurality of electrically conductive interconnects formed by a combination of mask-based and maskless lithography, in accordance with various embodiments.

[0005] FIGS. 3-12 illustrate various example stages in the manufacture of a device by using mask- based lithography to form a set of mask-based features in a first layer and subsequently using maskless lithography to form a set of maskless features in a layer above the first layer, in accordance with various embodiments.

[0006] FIGS. 13-21 illustrate various example stages in the manufacture of a device by using mask- based lithography to form a set of mask-based features in a first layer and subsequently using maskless lithography to form a set of maskless features in a layer below the first layer, in accordance with various embodiments.

[0007] FIGS. 22-25 illustrate various example stages in the manufacture of a device by using maskless lithography to add one or more features in the same layer where a set of features was formed using mask-based lithography, in accordance with various embodiments.

[0008] FIGS. 26-29 illustrate various example stages in the manufacture of a device by using maskless lithography to delete one or more features formed using mask-based lithography, in accordance with various embodiments. [0009] FIG. 30 illustrates an example tool for manufacturing devices by combining mask-based and maskless lithography, in accordance with various embodiments.

[0010] FIGS. 31A and 31B are top views of a wafer and dies that include one or more devices formed by combining mask-based and maskless lithography in accordance with any of the embodiments disclosed herein.

[0011] FIG. 32 is a cross-sectional side view of an integrated circuit (IC) device that may include one or more devices formed by combining mask-based and maskless lithography in accordance with any of the embodiments disclosed herein.

[0012] FIG. 33 is a cross-sectional side view of an IC device assembly that may include one or more devices formed by combining mask-based and maskless lithography in accordance with any of the embodiments disclosed herein.

[0013] FIG. 34 is a block diagram of an example computing device that may include one or more devices formed by combining mask-based and maskless lithography in accordance with any of the embodiments disclosed herein.

Detailed Description

[0014] Mask-based lithography, also referred to as "optical lithography" or "photolithography," refers to lithographic techniques where optical radiation is used to transfer a geometric pattern from a photomask to a light-sensitive emulsion, referred to as "photoresist" or simply "resist," on the substrate. A series of chemical treatments then either engraves the exposure pattern into the material under the photoresist or enables deposition of additional materials in the desired pattern upon the material under the photoresist.

[0015] Similar to mask-based lithography, maskless lithography also refers to lithographic techniques where radiation is used to expose a radiation-sensitive emulsion (i.e. resist). In contrast to mask-based lithography, in maskless lithography, the radiation is not projected from, or transmitted through, a photomask. Instead, the radiation is focused to a narrow beam which is then used to directly write the image into the resist, one or more pixels at a time. Some examples of maskless lithography include electron beam lithography, direct laser writing, focused ion beam lithography.

[0016] Maskless lithography generally suffers from a very low throughput but has the advantage of the ability to change the pattern to be written very quickly. Mask-based lithography is fast but inflexible because months may be required by tape out a new mask set.

[0017] Disclosed herein are methods for manufacturing devices by combining mask-based and maskless lithography. For example, in some embodiments, a method of forming a semiconductor device may include performing a mask-based lithographic process on a substrate having one or more layers disposed thereon to form a set of mask-based features in a first layer of the one or more layers and performing a maskless lithographic process on the substrate to form a set of maskless features. Such a method allows to benefit from the advantages of both mask-based and maskless lithographic techniques. For example, mask-based lithography may be used to form most of the features while maskless lithography may be used to modify, delete, or add a relatively small number of features. In this manner, high throughput may be achieved by employing mask-based lithography while providing the flexibility in the features allowed by the use of maskless lithography.

[0018] Devices formed by combining mask-based and maskless lithography as described herein may include e.g. interconnects and metallization stacks for providing electrical connectivity to one or more components associated with an integrated circuit (IC) or/and between various such components.

[0019] For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details or/and that the present disclosure may be practiced with only some of the described aspects. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations.

[0020] Further, references are made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense.

[0021] Various operations may be described as multiple discrete actions or operations in turn, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment.

Various additional operations may be performed, and/or described operations may be omitted in additional embodiments.

[0022] For the purposes of the present disclosure, the phrase "A and/or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between," when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. [0023] The description uses the phrases "in an embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. The terms "comprising," "including," "having," and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above," "below," "top," "bottom," and "side"; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0024] In the following detailed description, various aspects of the illustrative implementations will be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, as used herein, a "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide. In another example, a term

"interconnect" is used to describe any element formed of an electrically conductive material for providing electrical connectivity to one or more components associated with an IC or/and between various such components. In general, the "interconnect" may refer to both trenches (also sometimes referred to as "lines") and vias. In general, a term "trench" is used to describe an electrically conductive element isolated by an interconnect support layer typically comprising an interlayer low-k dielectric that is provided within the plane of an IC chip. Such trenches are typically stacked into several levels. On the other hand, the term "via" is used to describe an electrically conductive element that interconnects two or more trenches of different levels. To that end, vias are provided substantially perpendicularly to the plane of an IC chip. A via may interconnect two trenches in adjacent levels or two trenches in not adjacent levels. A term "metallization stack" refers to a stack of one or more interconnects for providing connectivity to different circuit components of an IC chip. The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 20% of a target value based on the context of a particular value as described herein or as known in the art.

[0025] In the following, various exemplary embodiments are described with reference to lithographic processing used for forming interconnects and metallization stacks for providing electrical connectivity to one or more components associated with an IC or/and between various such components. However, teachings provided herein are equally applicable, possibly with modifications that would be apparent to a person of ordinary skill in the art based on the descriptions provided herein, to nanopatterning of any structures, included in one or more components associated with an IC or/and between various such components for any purposes, using lithographic processes, all of which are within the scope of the present disclosure. For example, in some embodiments, lithographic processing described herein may be used to form nanostructured material comprising openings which are later filled with a precursor material for forming e.g. a low-k dielectric material within the openings.

[0026] In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be employed as part of a chipset for executing one or more related functions in a computer.

[0027] In the embodiments where at least some of the components associated with an integrated circuit are transistors, a plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the disclosure, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

[0028] Each MOS transistor may include a gate stack formed of at least two layers, a gate dielectric and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (S1O2) and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate interconnect support layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some

embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

[0029] The gate electrode layer may be formed on the gate dielectric layer and may include at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may include a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.

[0030] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[0031] In some implementations, when viewed as a cross-section of the transistor along the source- channel-drain direction, the gate electrode may be, or include, a "U"-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may be, or include, a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

[0032] In some implementations of the disclosure, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

[0033] As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion- implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

[0034] One or more interlayer dielectrics may be deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (S1O2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

[0035] FIG.1 is a flow diagram of an example method 100 of manufacturing a device, e.g. a metallization stack 110 shown in FIG.2, by combining mask-based and maskless lithography, in accordance with various embodiments. Although the operations of the method 100 are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture multiple patterns of features substantially simultaneously. In another example, operations may be performed in a different order, as needed.

[0036] At 102, a substrate with one or more layers provided thereon may be provided. Such a substrate may serve as an interconnect support layer in which a metallization stack having a plurality of interconnects may be provided. In some embodiments, the substrate provided at 102 may include a semiconductor substrate. In one implementation, the semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon-on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group lll-V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device may be built falls within the spirit and scope of the present disclosure.

[0037] At 104, a mask-based lithographic process is applied to form a set of features in the one or more layers on the substrate, features formed by the mask-based lithographic process referred to herein as "mask-based features." In general, application of a mask-based lithographic process involves providing a layer of photoresist over the upper layer over the substrate to be patterned, exposing the layer of photoresist through a mask to form a desired pattern of a plurality of openings is formed in the layer of photoresist, the openings exposing the underlying material of the upper layer on the substrate, and applying chemical processes, such as e.g. etching, to transfer the pattern in the layer of photoresist to the upper and possibly further layers provided over the substrate. In various embodiments, the photoresist could be either a positive photoresist or a negative photoresist. With a positive photoresist, the portions of photoresist exposed to light are removed, forming the openings in the layer of photoresist. With a negative photoresist, the portions of photoresist exposed to light remain while the portions of photoresist not exposed to light are removed, the latter forming the openings in the layer of photoresist.

[0038] At 106, a maskless lithographic process is applied to form a set of features in the one or more layers on the substrate, features formed by the maskless lithographic process referred to herein as "maskless features." In general, application of a maskless lithographic process involves providing a layer of resist over the upper layer over the substrate to be patterned, exposing the layer of resist to a relatively narrow beam of radiation, without using a mask, to form a desired pattern of one or more openings in the layer of resist, the openings exposing the underlying material of the upper layer on the substrate, and applying chemical processes, such as e.g. etching, to transfer the pattern in the layer of resist to the upper and possibly further layers provided over the substrate. Similar to photoresist, resist used in maskless lithography can be positive or negative. With a positive resist used in maskless lithography, the portions of resist exposed to radiation (e.g. electron beam or other charged particle beam) are removed, forming the openings in the layer of resist. With a negative resist used in maskless lithography, the portions of resist which were exposed to radiation remain while the portions of resist which were not exposed to light are removed, the latter forming the openings in the layer of resist.

[0039] Mask-based and maskless features formed in the one or more layers provided over the substrate may include e.g. openings in the one or more layers. In various embodiments, the mask- based and maskless features may be provided in a single layer, in different layers, or in combination of both. In some embodiments, at least some of the mask-based features may be provided in a layer either above (i.e. further away from the substrate) or below (i.e. closer to the substrate) a layer in which maskless features are provided, irrespective of which of mask-based or maskless lithography is performed first.

[0040] In further embodiments, the method 100 may include additional operations not specifically shown in FIG. 1, such as e.g. filling of the openings with electrically-conductive materials or providing additional layers over the substrate after either mask-based or maskless lithography has been applied.

[0041] FIG. 2 is a cross-sectional side view of a device 110 including a plurality of electrically conductive interconnects formed by a combination of mask-based and maskless lithography, in accordance with various embodiments. Such a device may be an example of a metallization stack for providing electrical connectivity to and between various components of an IC.

[0042] FIG. 2 illustrates a substrate having a layer 112 in which a plurality of initial features, labeled as features F01-F06, are provided. In the example shown in FIG. 2, the initial features F01-F06 are regions with a material 114. FIG. 2 also illustrates a layer 116, provided over the layer 112, in which a plurality of mask-based features, labeled as features F11-F16, are provided. In the example shown in FIG. 2, the mask-based features F11-F16 are openings filled with a material 118. FIG. 2 further illustrates a layer 120, provided over the layer 116, in which a plurality of maskless features, labeled as features F21-F23, are provided. In the example shown in FIG. 2, the maskless features F21-F23 are openings filled with a material 122.

[0043] In various embodiments, the layers 112, 116, and 120 may be layers of one or more dielectric materials, such as e.g. one or more ILD dielectrics described above, while the materials 114, 118, and 122 of the initial, mask-based, and maskless features may include one or more electrically conductive materials such as e.g. one or more bulk materials comprising aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), nickel (Ni), iron (Fe), and molybdenum (Mo) and/or one or more alloys comprising aluminum (Al), copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), manganese (Mn), magnesium (Mg), boron (B), phosphorus (P), nitrogen (N), carbon (C), and sulfur (S). In some embodiments, the layer 112 may be a substrate, such as e.g. any one of the substrates described above, or may be provided over such a substrate (in which case the substrate is not specifically shown in FIG. 2).

[0044] As shown in FIG. 2, each of the mask-based features F11-F16, corresponds to an associated one of the initial features F01-F06 by being provided in an overlapping manner with the associated initial feature. Thus, the mask-based feature Fn corresponds to the initial feature F01, the mask- based feature F12 corresponds to the initial feature F02, the mask-based feature F13 corresponds to the initial feature F03, and so on, until the mask-based feature Fi6 which corresponds to the initial feature F06. [0045] FIG. 2 further illustrates overlay errors of various features, indicated with distances dl, d2, d3, and d4. In general, overlay error characterizes the amount of, typically undesirable, offset between various features which are supposed to, ideally, aligned with one another. An overlay error may e.g. be quantified as a parameter indicative of the distance between the centerlines of two features which are supposed to be aligned. Presence of overlay errors is a typical challenge encountered when patterning extremely small vias with extremely small pitches by lithographic processes, especially when the pitches are around 70 nanometers (nm) or less and/or when the critical dimensions of the via openings are around 35 nm or less. The overlay between the vias and the underlying landing interconnects generally need to be controlled to high tolerances, e.g. on the order of a quarter of the via pitch, to make sure that proper electrical connections are made and to avoid creation of electrical connections where they are not supposed to be. As via pitches scale ever smaller over time, the overlay tolerances tend to scale with them.

[0046] As FIG. 2 illustrates, each of the mask-based features Fn-Fi6 has the same overlay error dl with respect to the corresponding one of the initial features F01-F06. The overlay error dl is shown in FIG. 2 as a distance between a centerline of each of the initial features F01-F06 (shown in FIG. 2 with a dotted line going through the center of each initial feature) and a centerline of each of the mask- based features F11-F16 (shown in FIG. 2 with a solid line going through the center of each mask-based feature). At the same time, different maskless features F21-F23 have different overlay errors - shown as d2, d3, and d4, with respect to the corresponding one of the initial features F01-F06. The overlay error d2 is shown in FIG. 2 as a distance between a centerline of the initial feature F01 (again, shown in FIG. 2 with a dotted line going through the center of this initial feature) and a centerline of the maskless feature F21 (shown in FIG. 2 with a solid line going through the center of this maskless feature). The overlay error d3 is shown in FIG. 2 as a distance between a centerline of the initial feature F04 (again, shown in FIG. 2 with a dotted line going through the center of this initial feature) and a centerline of the maskless feature F22 (shown in FIG. 2 with a solid line going through the center of this maskless feature). The overlay error d4 is shown in FIG. 2 as a distance between a centerline of the initial feature F05 (again, shown in FIG. 2 with a dotted line going through the center of this initial feature) and a centerline of the maskless feature F23 (shown in FIG. 2 with a solid line going through the center of this maskless feature).

[0047] FIG. 2 illustrating that all mask-based features have the same overlay error with respect to the initial features reflects the fact that, when a photomask is used, all features defined by the photomask will be misaligned by the same amount. On the other hand, the different overlay errors of various maskless features reflects the fact that each maskless feature is formed individually, by focusing a beam of radiation to form each feature, as is characteristic of maskless lithography. Thus, by analyzing a cross-section of a final device and quantifying overlay errors between various features as known in the art, features formed by mask-based lithography will be clearly distinguishable from features formed by maskless lithography.

[0048] FIG. 2 provides just one exemplary illustration of the differences between mask-based and maskless features formed using the method 100 described herein. Many modifications to this illustration are possible and are within the scope of the present disclosure. For example, while FIG. 2 illustrates 6 initial features, 6 mask-based features, and 3 maskless features, this is only for illustrative purposes and descriptions provided herein are applicable to the device 110 having any number of initial, mask-based features, and maskless features. In another example, while FIG. 2 illustrates that each mask-based feature has a corresponding initial feature, this is also only for illustrative purposes and descriptions provided herein are applicable to the device 110 having other mask-based features which do not have corresponding initial features, and vice versa. Similarly, while FIG. 2 illustrates that three maskless features have corresponding initial features, this is also only for illustrative purposes and descriptions provided herein are applicable to the device 110 having any number of maskless features, in any order, corresponding to the initial features. Still further, while the maskless features are described as corresponding to and with reference to their overlay error with respect to the initial features, they could also be described as corresponding to and with reference to their overlay error with respect to the mask-based features. For example, an overlay error of the maskless feature F21 may be measured as a difference between the centerline of the maskless feature F21 and the center line of the corresponding mask-based feature Fn, an overlay error of the maskless feature F22 may be measured as a difference between the centerline of the maskless feature F22 and the center line of the corresponding mask-based feature F14, and an overlay error of the maskless feature F23 may be measured as a difference between the centerline of the maskless feature F23 and the center line of the corresponding mask-based feature Fi ₅ . Even when quantified in this manner, the overlay errors of the individual maskless features will be

characteristically different from one another, in contrast to the same overlay errors of all mask- based features which have corresponding initial features.

[0049] Furthermore, while the cross-section shown in FIG. 2, as well as the cross-sections shown in FIGS. 3-30, are illustrated with precise right angles and straight lines, real-life cross sections of devices would typically reflect example real world process limitations in that the features often do not have precise right angles and straight lines. These example real word process limitations would allow further differentiation between features formed using a mask-based lithographic process and features formed using a maskless lithographic process. [0050] FIGS. 3-12 illustrate various example stages in the manufacture of a device by using mask- based lithography to form a set of mask-based features in a first layer and subsequently using maskless lithography to form a set of maskless features in a layer above the first layer, in accordance with various embodiments. FIGS. 3-12 may be viewed as illustrating manufacturing of a portion of a device such as the device 110 illustrated in FIG. 2. Therefore, reference numerals used in FIGS. 3-12 which are the same with reference numerals used in FIG. 2 are intended to illustrate the same or similar materials and layers as those described with reference to FIG. 2, and, therefore, in the interests of brevity, the description of these materials and layers is not repeated. A legend provided within a dashed box at the bottom of each page showing FIGS. 3-12 shows patterns used to indicate elements with different reference numerals illustrated in these figures, so that the figures themselves are not cluttered by many reference numerals.

[0051] FIG. 3 illustrates a cross-sectional view of an assembly 203 including a layer 116 provided over the initial layer 112. The initial layer 112 may include initial features as described above, but these are not shown in FIGS. 3-12 in order to not clutter these drawings. Discussions provided above with respect to the layer 116 and the initial layer 112 are applicable to FIGS. 3-12 and, therefore, in the interests of brevity, are not repeated here. The assembly 203 may be a substrate with one or more layers to be patterned as provided at 102 of the method 100.

[0052] FIG. 4 illustrates a cross-sectional view of an assembly 204 subsequent to providing a layer of photoresist 124 over the layer 116 of the assembly 203 shown in FIG. 3. The photoresist 124 may be a positive or negative resist and may include for example, poly(methyl methacrylate), poly(methyl glutarimide), DNQ/novolac, or SU-8 (an expoxy based negative resist). The layer of photoresist 124 as shown in FIG. 4 may be deposited by a casting process such as, for example, spin-coating. Spin coating may be performed e.g. at 1 to 10,000 rpm, including all values and ranges therein, for a time period in the range of e.g. 1 second to 10 seconds, including all values and ranges therein.

[0053] FIG. 5 illustrates a cross-sectional view of an assembly 205 subsequent to patterning the layer of photoresist 124 of the assembly 204 shown in FIG. 4. The photoresist 124 may be patterned by using a mask for optically projecting an image of a desired pattern onto the photoresist using photolithography, such as optical photolithography, immersion photolithography, deep ultraviolet (UV) lithography, extreme UV (EUV) lithography, or other techniques, wherein the wavelength of projected light may be up to 436 nm, including all values and ranges from 157 nm to 436 nm, such as 157 nm, 193 nm, 248 nm, etc. A developer, such as tetramethylammonium hydroxide TMAH (with or without surfactant) at a concentration of in the range of 0.1 N to 0.3 N, may be applied to the photoresist, such as by spin-coating, and portions of the photoresist may be removed to expose regions of the underlying layer 116 correlating to the desired pattern, as illustrated in FIG. 5 with openings 126 formed in the layer of photoresist 124 where the photoresist was removed. In case the photoresist 124 is a positive photoresist, the portions removed are those portions of the photoresist 124 which were exposed to light. In case the photoresist 124 is a negative photoresist, the portions removed are those portions of the photoresist 124 which were not exposed to light.

[0054] In some embodiments, baking of the substrate may occur before or after any of the above actions. For example, the substrate may be prebaked to remove surface water. In some embodiments, prebaking may be performed at a temperature in the range of 200° C to 400° C, including all values and ranges therein, for a time of 30 to 60 minutes, including all values and ranges therein. After application of a layer of the photoresist 124 as shown in FIG. 4, a post application bake may occur, wherein at least a portion of the solvents in the photoresist are driven off. A post application bake is, for example, performed at temperatures in the range of 70° C to 140° C, including all values and ranges therein, for a time period in the range of 60 seconds to 240 seconds, including all values and ranges therein. After patterning of the photoresist as shown in FIG. 5, the remaining resist may be hard baked at a temperature in the range of 100° C to 300° C, including all values and ranges therein, for a time period of 1 minute to 10 minutes, including all values and ranges therein.

[0055] FIG. 5 illustrates openings 126 formed in the layer of photoresist 124 where the photoresist was removed. The openings 126 expose regions of the underlying layer 116 correlating to the desired pattern. The exposed portions of the underlying layer 116 are then chemically etched, wherein the exposed portions of the surface of the layer 116 are removed until a desired depth is achieved, forming openings in the underlying layer 116. FIG. 6 illustrates a cross-sectional view of an assembly 206 subsequent to chemically etching the exposed portions of the surface of the layer 116 of the assembly 205 shown in FIG. 5 through the photoresist openings 126 to form openings 128 in the underlying layer 116. The chemical etch may include either anisotropic etch, as shown in FIG. 6, or isotropic etch (not shown in the figures), using any suitable etchant for etching the particular material or a combination of materials of the underlying layer 116, as known in the art.

[0056] FIG. 6 illustrates that the exposed portions of the underlying layer 116 are etched all the way through to the layer 112, to reflect the scenario where e.g. the openings 128 are supposed to be provided over and be connected to the initial features in the layer 112 (not shown in FIGS. 3-12, but shown in FIG. 2). However, in other embodiments, the exposed portions of the underlying layer 116 may be etched to any desired depth in the layer 116, not necessarily all the way through to the layer 112. FIG. 6 also illustrates that the remaining photoresist may, optionally, be removed via a process such as ashing, wherein the photoresist is exposed to oxygen or fluorine, which combines with the photoresist to form ash. [0057] FIG. 7 illustrates a cross-sectional view of an assembly 207 subsequent to filling the openings 128 in the layer 116 of the assembly 206 shown in FIG. 6 with a material 118, such as e.g. one or more of the electrically conductive materials described above. The material 118 may be deposited into the openings 128 using a vapor deposition method may be used, such as e.g. physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0058] PVD processes for depositing the via material such as the material 118 include, for example, magnetron sputtering, evaporative deposition or e-beam deposition. An example of physical vapor deposition includes supplying an inert gas, such as argon, at a flow rate in the range of 5 standard cubic centimeter per minute (seem) to 100 seem, including all values and ranges therein, into a process chamber, which is held at a pressure in the range of lxlO ^"1 torr to 10 ^"7 torr, including all values and ranges therein. The process chamber may include a workpiece, in this case the assembly 206 as shown in FIG. 6, and a metal source, called a target, formed of copper, aluminum or any other electrically conductive material that can be deposited by PVD. The metal source may be biased by a DC source rated in the range of 0.1 kW to 50 kW, including all values and ranges therein. The workpiece, or worktable upon which the workpiece is positioned, may also be biased by an AC source rated in the range of 0.1 kW to 1.5 kW, including all values and ranges therein. A plasma forms and is localized around the target due to magnets positioned proximal to or behind the target. The plasma bombards the target sputtering away the metal atoms as a vapor, which is then deposited on the workpiece. The process may continue for a time period in the range of 1 second to 100 seconds to allow growth of a layer of the material 118 including filling of the openings 128 with the material 118.

[0059] In alternative embodiments, CVD or ALD may be performed to fill the openings 128. In general, CVD or ALD is a chemical process in which one or more reactive precursor gases are introduced into a reaction chamber and directed towards a substrate in order to induce controlled chemical reactions that result in growth of a desired material on the substrate. The one or more reactive gases may be provided to the chamber at a flow rate of e.g. 5 seem to 500 seem, including all values and ranges therein. The reactive gas may be provided with a carrier gas, such as an inert gas, which may include, for example, argon. In some embodiments, the chamber may be maintained at a pressure in the range of 1 milliTorr to 100 milliTorr, including all values and ranges therein, and a temperature in the range of 100° C to 500° C, including all values and ranges therein. The substrate itself may also be heated. In some embodiments, the process may be plasma assisted where electrodes are provided within the process chamber and are used to ionize the gases.

Alternatively, plasma may be formed outside of the chamber and then supplied into the chamber. In the chamber, a layer of solid thin film material is deposited on the surface of the substrate due to reaction of the gas/gasses.

[0060] The reactive gas used to form the material 118 may be selected from, for example, Cu(ll)bis- hexafluoroacetylacetonate, l,5-cyclooctadiene-Cu(l)-hexafluoroacetylacetonate.

[0061] In some embodiments, the openings 128 may be filled with the material 118 by, first, forming a seed layer of the electrically conductive material (such as copper), in the range of 400 Angstroms to 600 Angstroms, such as 500 Angstroms, e.g. using a PVD process described above, followed by the electroplating of copper, during which the assembly 206 is placed to a solution of copper sulfate and sulfuric acid. A current density in the range of 25 mA/cm ² to 75 mA/ cm ² , such as 50 mA/ cm ² , may be applied for a time period of 30 seconds to 120 seconds, such as 60 seconds, resulting in the formation of copper as an example of the material 118.

[0062] As the foregoing description illustrates, during the deposition into the openings 128, the material 118 may be deposited over various surfaces of the layer 116, including the upper surfaces of the layer 116 (i.e. the surfaces surrounding the openings 128). Subsequently, planarization may be performed to expose these upper surfaces of the layer 116 so that the material 118 is provided only, or substantially, in the openings 128 as shown in FIG. 7. In various embodiments, planarization may be performed using either wet or dry planarization processes. In one embodiment, planarization is performed using chemical mechanical planarization (CM P), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface of the assembly 207 to expose upper surfaces 130, indicated in FIG. 7, of the layer 116.

[0063] Manufacturing stages illustrated in FIGS. 4-7 may be considered an example of creating a set of features using mask-based lithography at 104 of the method 100 shown in FIG. 1.

[0064] FIG. 8 illustrates a cross-sectional view of an assembly 208 subsequent to providing a layer 120 over the assembly 207 shown in FIG. 7. Discussions provided above with respect to the layer 120 are applicable to FIGS. 3-12 and, therefore, in the interests of brevity, are not repeated here.

[0065] FIG. 9 illustrates a cross-sectional view of an assembly 209 subsequent to providing a layer of resist 132 over the layer 120 of the assembly 208 shown in FIG. 8. The resist 132 may be a positive or negative resist and may include any material sensitive to the radiation used in maskless lithography (e.g. resist used in e-beam lithography). The layer of resist 132 as shown in FIG. 9 may be deposited by a casting process such as, for example, spin-coating. Spin coating may be performed e.g. at 1 to 10,000 rpm, including all values and ranges therein, for a time period in the range of e.g. 1 second to 10 seconds, including all values and ranges therein. [0066] FIG. 10 illustrates a cross-sectional view of an assembly 210 subsequent to patterning the layer of resist 132 of the assembly 209 shown in FIG. 9. The resist 132 may be patterned by focusing a narrow beam, e.g. an electron beam if maskless lithography involves e-beam lithography, to define a desired feature or a set of features in the resist 132. A suitable developer, similar to a developer used with the photoresist 124, may be applied to the resist 132 after the exposure, such as by spin- coating, and portions of the resist 132 may be removed to expose regions of the underlying layer 120 correlating to the pattern of the maskless exposure. This is illustrated in FIG. 10 with an openings 134 formed in the layer of resist 132 where the resist was removed. In case the resist 132 is a positive resist, the portions removed are those portions of the resist 132 which were exposed to the radiation of the maskless lithography, e.g. exposed to the e-beam. In case the resist 132 is a negative resist, the portions removed are those portions of the resist 132 which were not exposed to the radiation of the maskless lithography.

[0067] Similar to the discussions provided above for the photoresist 124, in some embodiments, baking of the substrate may occur before or after any of the above actions. For example, the substrate may be post-baked after application of a layer of the resist 132 as shown in FIG. 9, e.g. to drive off at least a portion of the solvents in the resist 132. A post application bake is, for example, performed at temperatures in the range of 70° C to 140° C, including all values and ranges therein, for a time period in the range of 60 seconds to 240 seconds, including all values and ranges therein. After patterning of the resist as shown in FIG. 10, the remaining resist may be hard baked at a temperature in the range of 100° C to 300° C, including all values and ranges therein, for a time period of 1 minute to 10 minutes, including all values and ranges therein.

[0068] FIG. 10 illustrates the opening 134 formed in the layer of resist 132 where the resist was removed. The opening 134 exposes a region of the underlying layer 120 correlating to the desired pattern created by maskless lithographic exposure. The exposed portion of the underlying layer 120 is then chemically etched, wherein the exposed portions of the surface of the layer 120 are removed until a desired depth is achieved, forming openings in the underlying layer 120. FIG. 11 illustrates a cross-sectional view of an assembly 211 subsequent to chemically etching the exposed portions of the surface of the layer 120 of the assembly 210 shown in FIG. 10 through the resist opening 134 to form a corresponding opening 136 in the underlying layer 120. The chemical etch may include either anisotropic etch, as shown in FIG. 11, or isotropic etch (not shown in the figures), using any suitable etchant for etching the particular material or a combination of materials of the underlying layer 120, as known in the art.

[0069] FIG. 11 illustrates that the exposed portion of the underlying layer 120 is etched all the way through to the underlying layer 116 with the openings 128 filled with the material 118, to reflect the scenario where e.g. the opening 134 are supposed to be provided over and be connected to the mask-based features in the layer 116. However, in other embodiments, the exposed portions of the underlying layer 120 may be etched to any desired depth in the layer 120, not necessarily all the way through. FIG. 11 also illustrates that the remaining resist 132 may, optionally, be removed, e.g. using ashing as described above.

[0070] FIG. 12 illustrates a cross-sectional view of an assembly 212 subsequent to filling the opening 136 in the layer 120 of the assembly 211 shown in FIG. 11 with a material 122, such as e.g. one or more of the electrically conductive materials described above. The material 122 may be deposited into the opening 134 using any of the methods described above for depositing the material 118, possibly followed by the planarization to remove the overburden of the material 122 and expose upper surfaces 138 of the material layer 120 surrounding the opening 136 filled with the material 122.

[0071] Manufacturing stages illustrated in FIGS. 9-12 may be considered an example of creating a set of features using maskless lithography at 106 of the method 100 shown in FIG. 1.

[0072] While FIGS. 3-12 illustrate how maskless features may be formed in a layer above the layer in which mask-based features are formed, FIGS. 13-21 illustrate the opposite example where maskless features are formed in a layer below the layer in which mask-based features were formed.

[0073] As described above, the device 110 illustrated in FIG. 2 may include many modifications compared to what is shown in FIG. 2. One of such modifications is that the layer in which maskless features are formed may be provided below the layer in which the mask-based features are formed, as opposed to being provided above the mask-based layer as shown in FIG. 2. FIGS. 13-21 may be viewed as illustrating manufacturing of a portion of such a modified device 110. Therefore, reference numerals used in FIGS. 13-21 which are the same with reference numerals used in FIG. 2 are intended to illustrate the same or similar materials and layers as those described with reference to FIG. 2, and, therefore, in the interests of brevity, the description of these materials and layers is not repeated. Furthermore, reference numerals used in FIGS. 13-21 which are the same with reference numerals used in FIGS. 3-12 are intended to illustrate the same or similar materials and layers as those described with reference to FIGS. 3-12, and, therefore, in the interests of brevity, the description of these materials and layers is also not repeated. A legend provided within a dashed box at the bottom of each page showing FIGS. 13-21 shows patterns used to indicate elements with different reference numerals illustrated in these figures, so that the figures themselves are not cluttered by many reference numerals.

[0074] FIG. 13 illustrates a cross-sectional view of an assembly 213 including a layer 116 provided over a layer 120, where the layer 120 is provided over the initial layer 112. The initial layer 112 may include initial features as described above, but these are not shown in FIGS. 13-21 in order to not clutter these drawings. Discussions provided above with respect to the layers 112, 116, and 120 are applicable to FIGS. 13-21 and, therefore, in the interests of brevity, are not repeated here. The assembly 213 may be a substrate with one or more layers to be patterned as provided at 102 of the method 100.

[0075] FIG. 14 illustrates a cross-sectional view of an assembly 214 subsequent to providing a layer of photoresist 124 over the layer 116 of the assembly 213 shown in FIG. 13. Discussions provided above with respect to providing the layer of photoresist 124 for the assembly 204 shown in FIG. 4 are applicable to FIG. 14.

[0076] FIG. 15 illustrates a cross-sectional view of an assembly 215 subsequent to patterning the layer of photoresist 124 of the assembly 214 shown in FIG. 14. Discussions provided above with respect to patterning the layer of photoresist 124 to form the assembly 205 shown in FIG. 5 are applicable to FIG. 15. FIG. 15 illustrates openings 140 formed in the layer of photoresist 124 where the photoresist was removed. The openings 140 expose regions of the underlying layer 116 correlating to the desired pattern. The exposed portions of the underlying layer 116 are then chemically etched, wherein the exposed portions of the surface of the layer 116 are removed until a desired depth is achieved, forming openings in the underlying layer 116. FIG. 16 illustrates a cross- sectional view of an assembly 216 subsequent to chemically etching the exposed portions of the surface of the layer 116 of the assembly 215 shown in FIG. 15 through the photoresist openings 140 to form openings 142 in the underlying layer 116. Discussions provided above with respect to etching the layer 116 to of the assembly 205 shown in FIG. 5 are applicable to FIGS. 15 and 16.

[0077] FIG. 16 illustrates that all of the exposed portions of the underlying layer 116 are etched all the way through to the layer 120, to account for the fact that, in a subsequent process, the underlying layer 120 will also be etched via at least some of the openings 142. However, in other embodiments, at least some of the exposed portions of the underlying layer 116 may be etched to any desired depth in the layer 116, not necessarily all the way through to the layer 120. FIG. 16 also illustrates that the remaining photoresist 124 may, optionally, be removed, as described above.

[0078] Manufacturing stages illustrated in FIGS. 14-16 may be considered an example of creating a set of features using mask-based lithography at 104 of the method 100 shown in FIG. 1.

[0079] FIG. 17 illustrates a cross-sectional view of an assembly 217 subsequent to filling the openings 142 and covering the upper surface of the layer 116 of the assembly 216 shown in FIG. 16 with the resist 132 used for the subsequent maskless lithography. Discussions provided above with respect to providing the layer of photoresist 132 are applicable to FIG. 17. [0080] FIG. 18 illustrates a cross-sectional view of an assembly 218 subsequent to patterning the layer of resist 132 of the assembly 217 shown in FIG. 17. Discussions provided above with respect to patterning the resist 132 to form an opening 134 as shown in FIG. 10 is applicable to patterning the resist 132 to form an opening 144 as shown in FIG. 18. Similar to the opening 134 shown in FIG. 10, the opening 144 shown in FIG. 18 exposes a region of the underlying layer 120 correlating to the desired pattern created by maskless lithographic exposure, except that now the opening 144 happens to be within the opening 142 formed in the layer 116 in which mask-based features were formed. The exposed portion of the underlying layer 120 is then chemically etched, wherein the portions of the surface of the layer 120 exposed in the opening 144 are removed until a desired depth is achieved, forming an opening in the underlying layer 120. FIG. 19 illustrates a cross- sectional view of an assembly 219 subsequent to chemically etching the exposed portions of the surface of the layer 120 of the assembly 218 shown in FIG. 18 through the resist opening 144 to form a corresponding opening 146 in the underlying layer 120. The chemical etch may include either anisotropic etch, as shown in FIG. 19, or isotropic etch (not shown in the figures), using any suitable etchant for etching the particular material or a combination of materials of the underlying layer 120, as known in the art.

[0081] FIG. 20 illustrates a cross-sectional view of an assembly 220 subsequent to removing the remaining resist 132 from the assembly 219 shown in FIG. 19, using e.g. the ashing process as described above.

[0082] FIG. 21 illustrates a cross-sectional view of an assembly 221 subsequent to filling the openings 142 and 146 in the layers 116and 120 of the assembly 220 shown in FIG. 20 with a material 118, such as e.g. one or more of the electrically conductive materials described above. To that end, depositions processes as described above for the deposition of the 118 may be used to form the assembly 221. Subsequently, planarization as described above may be performed to remove the overburden of the material 118 and expose upper surfaces 148 of the material layer 116

surrounding the opening 142 filled with the material 118, as also shown in FIG. 21.

[0083] Manufacturing stages illustrated in FIGS. 17-21 may be considered an example of creating a set of features using maskless lithography at 106 of the method 100 shown in FIG. 1.

[0084] While FIGS. 3-12 and FIGS. 13-21 illustrate how maskless features and mask-based features may be formed in different layers, FIGS. 22-25 and FIGS. 26-29 illustrate two different examples of how maskless and mask-based lithographic processes may be combined to modify features in a single layer. [0085] FIGS. 22-25 illustrate various example stages in the manufacture of a device by using maskless lithography to add one or more features in the same layer where a set of features was formed using mask-based lithography, in accordance with various embodiments.

[0086] As described above, the device 110 illustrated in FIG. 2 may include many modifications compared to what is shown in FIG. 2. One of such modifications is that the maskless features may be formed within the same layer in which the mask-based features are formed, as opposed to being provided above the mask-based layer as shown in FIG. 2or below the mask-based layer as shown in FIG. 21. FIGS. 22-25 may be viewed as illustrating manufacturing of a portion of such a modified device 110. Therefore, reference numerals used in FIGS. 22-25 which are the same as the reference numerals used in FIG. 2 are intended to illustrate the same or similar materials and layers as those described with reference to FIG. 2, and, therefore, in the interests of brevity, the description of these materials and layers is not repeated. Furthermore, reference numerals used in FIGS. 22-25 which are the same with reference numerals used in FIGS. 3-12 are intended to illustrate the same or similar materials and layers as those described with reference to FIGS. 3-12, and, therefore, in the interests of brevity, the description of these materials and layers is also not repeated. A legend provided within a dashed box at the bottom of each page showing FIGS. 22-25 shows patterns used to indicate elements with different reference numerals illustrated in these figures, so that the figures themselves are not cluttered by many reference numerals.

[0087] FIGS. 22-25 may be viewed as a continuation of a manufacturing process similar to that shown in FIGS. 13-17 except that the layer 120 shown in FIGS. 13-17 does not have to be there, and is not shown, in FIGS. 22-25 because only the layer 116 is being patterned. Thus, in a manufacturing process illustrated in FIGS. 22-25, the layer 116 has already been patterned using mask-based lithography to form openings similar to the openings 142 described above in the layer 116. After that, resist 132 to be used for maskless lithography is provided.

[0088] FIG. 22 illustrates a cross-sectional view of an assembly 222 subsequent to patterning the layer of resist 132 of an assembly such as the assembly 217 shown in FIG. 17 but without the layer 120. Discussions provided above with respect to patterning the resist 132 to form an opening 144 as shown in FIG. 18 is applicable to patterning the resist 132 to form an opening 150 as shown in FIG. 22. Similar to the opening 144 shown in FIG. 18, the opening 150 shown in FIG. 22 exposes a region of the underlying layer 112 correlating to the desired pattern created by maskless lithographic exposure, including that the opening 150 happens to be within the opening 142 formed in the layer 116 in which mask-based features were formed.

[0089] The opening 150 is then filled with a material 152, which may e.g. be a dielectric material as any of the ILD materials described above, which may be done as known in the art. FIG. 23 illustrates a cross-sectional view of an assembly 223 subsequent to filling the opening 150 in the resist 132 of the assembly 222 shown in FIG. 22 with the material 152. The remaining resist 132 and the material 152 may then be planarized, as described above, to expose the upper surfaces of the layer 116 (not shown in FIG. 23).

[0090] FIG. 24 illustrates a cross-sectional view of an assembly 224 subsequent to removing the remaining resist 132 from the assembly 223 shown in FIG. 23, using e.g. the ashing process as described above. FIG. 24 illustrates that, after the resist 132 is removed and the material 152 filled into the opening 150 is planarized, a feature 154 is formed within the left opening 142 shown in FIG. 24, dividing the left opening 142 into two openings - an opening 156 and an opening 158.

[0091] FIG. 25 illustrates a cross-sectional view of an assembly 225 subsequent to filling the openings 142, 156, and 158 in the layer 116 of the assembly 224 shown in FIG. 24 with a material 118, such as e.g. one or more of the electrically conductive materials described above. To that end, depositions processes as described above for the deposition of the 118 may be used to form the assembly 225. Subsequently, planarization as described above may be performed to remove the overburden of the material 118 and expose upper surfaces 160 of the material layer 116, as also shown in FIG. 21.

[0092] Manufacturing stages illustrated in FIGS. 22-25 may be considered an example of creating a set of features using maskless lithography at 106 of the method 100 shown in FIG. 1.

[0093] FIGS. 26-29 illustrate various example stages in the manufacture of a device by using maskless lithography to delete one or more features formed using mask-based lithography, in accordance with various embodiments.

[0094] FIGS. 26-29 may be viewed as a continuation of a manufacturing process similar to that shown in FIGS. 13-17 except that the layer 120 shown in FIGS. 13-17 does not have to be there, and is not shown, in FIGS. 26-29 because only the layer 116 is being patterned. Thus, in a manufacturing process illustrated in FIGS. 26-29, the layer 116 has already been patterned using mask-based lithography to form openings similar to the openings 142 described above in the layer 116. After that, resist 132 to be used for maskless lithography is provided.

[0095] FIG. 26 illustrates a cross-sectional view of an assembly 226 subsequent to patterning the layer of resist 132 of an assembly such as the assembly 217 shown in FIG. 17 but without the layer 120. Discussions provided above with respect to patterning the resist 132 to form an opening 144 as shown in FIG. 18 is applicable to patterning the resist 132 to form an opening 162 as shown in FIG. 26. Similar to the opening 144 shown in FIG. 18, the opening 162 shown in FIG. 26 exposes a region of the underlying layer 112 correlating to the desired pattern created by maskless lithographic exposure, but now the opening 162 includes the left opening 142 of FIG. 26 formed in the layer 116 in which mask-based features were formed.

[0096] The opening 162 is then filled with a material 164, which may e.g. be a dielectric material as any of the ILD materials described above, which may be done as known in the art. FIG. 27 illustrates a cross-sectional view of an assembly 227 subsequent to filling the opening 162 in the resist 132 of the assembly 226 shown in FIG. 26 with the material 164.

[0097] FIG. 28 illustrates a cross-sectional view of an assembly 228 subsequent to removing the remaining resist 132 and planarizing the material 164 of the assembly 227 shown in FIG. 27, using e.g. the ashing and planarization processes as described above. FIG. 28 illustrates that, after the resist 132 is removed and the material 164 filled into the opening 162 is planarized, the left opening 142 in the layer 116, i.e. one of the mask-based features, is eliminated.

[0098] FIG. 29 illustrates a cross-sectional view of an assembly 229 subsequent to filling the remaining openings 142 in the layer 116 of the assembly 228 shown in FIG. 28 with a material 118, such as e.g. one or more of the electrically conductive materials described above. To that end, depositions processes as described above for the deposition of the 118 may be used to form the assembly 229. Subsequently, planarization as described above may be performed to remove the overburden of the material 118 and expose upper surfaces 166 of the material layer 116, as also shown in FIG. 29.

[0099] Manufacturing stages illustrated in FIGS. 26-29 may be considered an example of creating a set of features using maskless lithography at 106 of the method 100 shown in FIG. 1.

[0100] The cross-sections of devices shown in FIGS. 2-29 illustrate only some examples of combining mask-based and maskless lithography. In other embodiments, substantially more complicated patterns may be created by repeating some of the manufacturing stages described with reference to FIGS. 3-29, or/and running some manufacturing stages in parallel, all of which being within the scope of the present disclosure. For example, devices may be created with maskless lithography is used to add new features in the same layer as the mask-based features, delete some of the mask-based features, modify dimensions of some of the mask-based features, and add maskless features in layers above or/and below the layer with the mask-based features. In various embodiments, the devices described herein may include further layers not shown in FIGS. 2-29, such as e.g. one or more interfacial layers, layers promoting adhesion between various materials, diffusion barrier layers, and so on.

[0101] FIG. 30 illustrates an example tool/assembly 1000 for manufacturing devices by combining mask-based and maskless lithography, in accordance with various embodiments. As shown in FIG. 30, the tool 1000 may include lithographic equipment 1002 for performing at least portions of mask- based lithography (e.g. optical exposure using a mask), lithographic equipment 1004 for performing at least portions of maskless lithography (e.g. exposure to a narrow radiation beam without using a mask), and a controller 1006 for controlling operation of the equipment 1002 and/or 1004 to control and/or enable functionalities described herein. To that end, in some embodiments, the controller 1006 may include at least a processor 1008 and a memory 1010, configured to implement various methods for controlling the application of mask-based and maskless lithographic techniques as described herein. The memory 1010 may store a computer program comprising computer-readable instructions which, when executed on the processor 1008, are configured to control operation of the equipment 1002 and/or 1004 to control and/or enable functionalities described herein. Thus, some aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable medium(s), preferably non-transitory, having computer readable program code embodied, e.g., stored, thereon. In various embodiments, such a computer program may, for example, be downloaded (updated) to the existing devices and systems (e.g. to the existing controllers of lithographic equipment, etc.) or be stored upon manufacturing of these devices and systems.

[0102] The devices such as e.g. metallization stacks disclosed herein may be included in any suitable electronic device. FIGS. 31-34 illustrate various examples of apparatuses that may include one or more of the metallization stacks disclosed herein.

[0103] FIGS. 31A-B are top views of a wafer 1100 and dies 1102 that may include one or more devices, such as e.g. metallization stacks, formed by combining mask-based and maskless lithography in accordance with any of the embodiments disclosed herein. The wafer 1100 may be composed of semiconductor material and may include one or more dies 1102 having IC structures formed on a surface of the wafer 1100. Each of the dies 1102 may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including one or more components that include one or more devices as shown in FIGS. 2-29). After the fabrication of the semiconductor product is complete (e.g., after manufacture of one or more devices, such as e.g. metallization stacks, formed by combining mask-based and maskless lithography in a particular electronic component, e.g. in a transistor or in a memory device), the wafer 1100 may undergo a singulation process in which each of the dies 1102 is separated from one another to provide discrete "chips" of the semiconductor product. In particular, devices that include one or more devices formed by combining mask-based and maskless lithography as disclosed herein may take the form of the wafer 1100 (e.g., not singulated) or the form of the die 1102 (e.g., singulated). The die 1102 may include one or more transistors (e.g., one or more of the transistors 1240 of FIG. 32, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components (e.g., one or more of the interconnects discussed herein, which may take the form of any of the assemblies described herein). In some embodiments, the wafer 1100 or the die 1102 may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1102. For example, a memory array formed by multiple memory devices may be formed on a same die 1102 as a processing device (e.g., the processing device 1402 of FIG. 34) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

[0104] FIG. 32 is a cross-sectional side view of an IC device 1200 that may include one or more devices, e.g. metallization stacks, formed by combining mask-based and maskless lithography in accordance with any of the embodiments disclosed herein. The IC device 1200 may be formed on a substrate 1202 (e.g., the wafer 1100 of FIG. 31A) and may be included in a die (e.g., the die 1102 of FIG. 31B). The substrate 1202 may be any substrate as described herein. The substrate 1202 may be part of a singulated die (e.g., the dies 1102 of FIG. 31B) or a wafer (e.g., the wafer 1100 of FIG. 31A).

[0105] The IC device 1200 may include one or more device layers 1204 disposed on the substrate 1202. The device layer 1204 may include features of one or more transistors 1240 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1202. The device layer 1204 may include, for example, one or more source and/or drain (S/D) regions 1220, a gate 1222 to control current flow in the transistors 1240 between the S/D regions 1220, and one or more S/D contacts 1224 to route electrical signals to/from the S/D regions 1220. The transistors 1240 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1240 are not limited to the type and configuration depicted in FIG. 32 and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all- around gate transistors, such as nanoribbon and nanowire transistors.

[0106] Each transistor 1240 may include a gate 1222 formed of at least two layers, a gate electrode layer and a gate dielectric layer.

[0107] The gate electrode layer may be formed on the gate interconnect support layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor, respectively. In some

implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer or/and an adhesion layer.

[0108] For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 electron Volts (eV) and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

[0109] In some embodiments, when viewed as a cross section of the transistor 1240 along the source-channel-drain direction, the gate electrode may be formed as a U-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may be implemented as a combination of U-shaped structures and planar, non-U- shaped structures. For example, the gate electrode may be implemented as one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers. In some embodiments, the gate electrode may consist of a V-shaped structure (e.g., when a fin of a finFET transistor does not have a "flat" upper surface, but instead has a rounded peak).

[0110] Generally, the gate dielectric layer of a transistor 1240 may include one layer or a stack of layers, and the one or more layers may include silicon oxide, silicon dioxide, and/or a high-k dielectric material. The high-k dielectric material included in the gate dielectric layer of the transistor 1240 may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used. [0111] The S/D regions 1220 may be formed within the substrate 1202 adjacent to the gate 1222 of each transistor 1240, using any suitable processes known in the art. For example, the S/D regions 1220 may be formed using either an implantation/diffusion process or a deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion- implanted into the substrate 1202 to form the S/D regions 1220. An annealing process that activates the dopants and causes them to diffuse farther into the substrate 1202 may follow the ion implantation process. In the latter process, an epitaxial deposition process may provide material that is used to fabricate the S/D regions 1220. In some implementations, the S/D regions 1220 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some

embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1220 may be formed using one or more alternate semiconductor materials such as germanium or a group lll-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1220. In some embodiments, an etch process may be performed before the epitaxial deposition to create recesses in the substrate 1202 in which the material for the S/D regions 1220 is deposited.

[0112] Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the transistors 1240 of the device layer 1204 through one or more interconnect layers disposed on the device layer 1204 (illustrated in FIG. 32 as interconnect layers 1206-1210). For example, electrically conductive features of the device layer 1204 (e.g., the gate 1222 and the S/D contacts 1224) may be electrically coupled with the interconnect structures 1228 of the interconnect layers 1206-1210. The one or more interconnect layers 1206-1410 may form an interlayer dielectric (ILD) stack 1219 of the IC device 1200. One or more of the interconnect layers 1206-1210 may take the form of any of the embodiments of the devices formed by combining mask-based and maskless lithography disclosed herein, for example any of the embodiments discussed herein with reference to any of the assemblies shown in FIGS. 2-29, or any combination of such assemblies.

[0113] The interconnect structures 1228 may be arranged within the interconnect layers 1206-1410 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 1228 depicted in FIG. 33). Although a particular number of interconnect layers 1206-1410 is depicted in FIG. 33, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

[0114] In some embodiments, the interconnect structures 1228 may include trench structures 1228a (sometimes referred to as "lines") and/or via structures 1228b (sometimes referred to as "holes") filled with an electrically conductive material such as a metal. The trench structures 1228a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate 1202 upon which the device layer 1204 is formed. For example, the trench structures 1228a may route electrical signals in a direction in and out of the page from the perspective of FIG. 32. The via structures 1228b may be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate 1202 upon which the device layer 1204 is formed. In some embodiments, the via structures 1228b may electrically couple trench structures 1228a of different interconnect layers 1206-1210 together.

[0115] The interconnect layers 1206-1210 may include a dielectric material 1226 disposed between the interconnect structures 1228, as shown in FIG. 32. The dielectric material 1226 may take the form of any of the embodiments of the dielectric material provided between the interconnects of the metallization stacks disclosed herein, for example any of the embodiments discussed herein with reference to the ILD materials, or any of the assemblies shown in FIGS. 2-29.

[0116] In some embodiments, the dielectric material 1226 disposed between the interconnect structures 1228 in different ones of the interconnect layers 1206-1210 may have different compositions. In other embodiments, the composition of the dielectric material 1226 between different interconnect layers 1206-1210 may be the same.

[0117] A first interconnect layer 1206 (referred to as Metal 1 or "M l") may be formed directly on the device layer 1204. In some embodiments, the first interconnect layer 1206 may include trench structures 1228a and/or via structures 1228b, as shown. The trench structures 1228a of the first interconnect layer 1206 may be coupled with contacts (e.g., the S/D contacts 1224) of the device layer 1204.

[0118] A second interconnect layer 1208 (referred to as Metal 2 or "M 2") may be formed directly on the first interconnect layer 1206. In some embodiments, the second interconnect layer 1208 may include via structures 1228b to couple the trench structures 1228a of the second interconnect layer 1208 with the trench structures 1228a of the first interconnect layer 1206. Although the trench structures 1228a and the via structures 1228b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 1208) for the sake of clarity, the trench structures 1228a and the via structures 1228b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.

[0119] A third interconnect layer 1210 (referred to as Metal 3 or "M3") (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1208 according to similar techniques and configurations described in connection with the second interconnect layer 1208 or the first interconnect layer 1206. [0120] The IC device 1200 may include a solder resist material 1234 (e.g., polyimide or similar material) and one or more bond pads 1236 formed on the interconnect layers 1206-1210. The bond pads 1236 may be electrically coupled with the interconnect structures 1228 and configured to route the electrical signals of the transistor(s) 1240 to other external devices. For example, solder bonds may be formed on the one or more bond pads 1236 to mechanically and/or electrically couple a chip including the IC device 1200 with another component (e.g., a circuit board). The IC device 1200 may have other alternative configurations to route the electrical signals from the interconnect layers 1206-1210 than depicted in other embodiments. For example, the bond pads 1236 may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components.

[0121] FIG. 33 is a cross-sectional side view of an IC device assembly 1300 that may include components having or being associated with (e.g. being electrically connected by means of) one or more devices formed by combining mask-based and maskless lithography in accordance with any of the embodiments disclosed herein. The IC device assembly 1300 includes a number of components disposed on a circuit board 1302 (which may be, e.g., a motherboard). The IC device assembly 1300 includes components disposed on a first face 1340 of the circuit board 1302 and an opposing second face 1342 of the circuit board 1302; generally, components may be disposed on one or both faces 1340 and 1342. In particular, any suitable ones of the components of the IC device assembly 1300 may include any of the assemblies or a combination of assemblies disclosed herein.

[0122] In some embodiments, the circuit board 1302 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1302. In other embodiments, the circuit board 1302 may be a non-PCB substrate.

[0123] The IC device assembly 1300 illustrated in FIG. 33 includes a package-on-interposer structure 1336 coupled to the first face 1340 of the circuit board 1302 by coupling components 1316. The coupling components 1316 may electrically and mechanically couple the package-on-interposer structure 1336 to the circuit board 1302, and may include solder balls (as shown in FIG. 33), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

[0124] The package-on-interposer structure 1336 may include an IC package 1320 coupled to an interposer 1304 by coupling components 1318. The coupling components 1318 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1316. Although a single IC package 1320 is shown in FIG. 33, multiple IC packages may be coupled to the interposer 1304; indeed, additional interposers may be coupled to the interposer 1304. The interposer 1304 may provide an intervening substrate used to bridge the circuit board 1302 and the IC package 1320. The IC package 1320 may be or include, for example, a die (the die 1102 of FIG. 31B), an IC device (e.g., the IC device 1200 of FIG. 32), or any other suitable component. Generally, the interposer 1304 may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer 1304 may couple the IC package 1320 (e.g., a die) to a ball grid array (BGA) of the coupling components 1316 for coupling to the circuit board 1302. In the embodiment illustrated in FIG. 33, the IC package 1320 and the circuit board 1302 are attached to opposing sides of the interposer 1304; in other embodiments, the IC package 1320 and the circuit board 1302 may be attached to a same side of the interposer 1304. In some

embodiments, three or more components may be interconnected by way of the interposer 1304.

[0125] The interposer 1304 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer 1304 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group lll-V and group IV materials. The interposer 1304 may include metal interconnects 1308 and vias 1310, including but not limited to through-silicon vias (TSVs) 1306. The interposer 1304 may further include embedded devices 1314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio-frequency ( F) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1304. The package-on-interposer structure 1336 may take the form of any of the package-on-interposer structures known in the art.

[0126] The IC device assembly 1300 may include an IC package 1324 coupled to the first face 1340 of the circuit board 1302 by coupling components 1322. The coupling components 1322 may take the form of any of the embodiments discussed above with reference to the coupling components 1316, and the IC package 1324 may take the form of any of the embodiments discussed above with reference to the IC package 1320.

[0127] The IC device assembly 1300 illustrated in FIG. 33 includes a package-on-package structure 1334 coupled to the second face 1342 of the circuit board 1302 by coupling components 1328. The package-on-package structure 1334 may include an IC package 1326 and an IC package 1332 coupled together by coupling components 1330 such that the IC package 1326 is disposed between the circuit board 1302 and the IC package 1332. The coupling components 1328 and 1330 may take the form of any of the embodiments of the coupling components 1316 discussed above, and the IC packages 1326 and 1332 may take the form of any of the embodiments of the IC package 1320 discussed above. The package-on-package structure 1334 may be configured in accordance with any of the package-on-package structures known in the art.

[0128] FIG. 34 is a block diagram of an example computing device 1400 that may include one or more components including one or more devices formed by combining mask-based and maskless lithography in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device 1400 may include a die (e.g., the die 1102 of FIG. 31B) having one or more assemblies as shown in FIGS. 2-29, or a combination of such assemblies. Any one or more of the components of the computing device 1400 may include, or be included in, an IC device 1200 (FIG. 32). Any one or more of the components of the computing device 1400 may include, or be included in, an IC device assembly 1300 (FIG. 33).

[0129] A number of components are illustrated in FIG. 34 as included in the computing device 1400, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device 1400 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

[0130] Additionally, in various embodiments, the computing device 1400 may not include one or more of the components illustrated in FIG. 34, but the computing device 1400 may include interface circuitry for coupling to the one or more components. For example, the computing device 1400 may not include a display device 1406, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 1406 may be coupled. In another set of examples, the computing device 1400 may not include an audio input device 1424 or an audio output device 1408, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device 1424 or audio output device 1408 may be coupled.

[0131] The computing device 1400 may include a processing device 1402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device 1402 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device 1400 may include a memory 1404, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, the memory 1404 may include memory that shares a die with the processing device 1402. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).

[0132] In some embodiments, the computing device 1400 may include a communication chip 1412 (e.g., one or more communication chips). For example, the communication chip 1412 may be configured for managing wireless communications for the transfer of data to and from the computing device 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.

[0133] The communication chip 1412 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UM B) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for

Microwave Access, which is a certification mark for products that pass conformity and

interoperability tests for the IEEE 802.16 standards. The communication chip 1412 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1412 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1412 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1412 may operate in accordance with other wireless protocols in other embodiments. The computing device 1400 may include an antenna 1422 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).

[0134] In some embodiments, the communication chip 1412 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1412 may include multiple communication chips. For instance, a first communication chip 1412 may be dedicated to shorter-range wireless

communications such as Wi-Fi or Bluetooth, and a second communication chip 1412 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1412 may be dedicated to wireless communications, and a second communication chip 1412 may be dedicated to wired communications.

[0135] The computing device 1400 may include battery/power circuitry 1414. The battery/power circuitry 1414 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device 1400 to an energy source separate from the computing device 1400 (e.g., AC line power).

[0136] The computing device 1400 may include a display device 1406 (or corresponding interface circuitry, as discussed above). The display device 1406 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.

[0137] The computing device 1400 may include an audio output device 1408 (or corresponding interface circuitry, as discussed above). The audio output device 1408 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.

[0138] The computing device 1400 may include an audio input device 1424 (or corresponding interface circuitry, as discussed above). The audio input device 1424 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

[0139] The computing device 1400 may include a global positioning system (GPS) device 1418 (or corresponding interface circuitry, as discussed above). The GPS device 1418 may be in

communication with a satellite-based system and may receive a location of the computing device 1400, as known in the art.

[0140] The computing device 1400 may include an other output device 1410 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. [0141] The computing device 1400 may include an other input device 1420 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1420 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0142] The computing device 1400 may have any desired form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 1400 may be any other electronic device that processes data.

[0143] The following paragraphs provide various examples of the embodiments disclosed herein.

[0144] Example 1 provides a method for forming a device. The method includes performing a mask-based lithographic process on a substrate having one or more layers disposed thereon to form a set of mask-based features in a first layer of the one or more layers and performing a maskless lithographic process on the substrate to form a set of maskless features.

[0145] Example 2 provides the method according to Example 1, where the one or more layers include two or more layers, each feature of the set of mask-based features at least partially overlaps a corresponding feature of a set of initial features provided in a second layer of the two or more layers, the second layer disposed between the first layer and the substrate and has a first overlay error with respect to the corresponding feature of the set of initial features. Furthermore, a first feature of the set of maskless features has a second overlay error with respect to a corresponding first feature of the set of initial features and a second feature of the set of maskless features has a third overlay error with respect to a corresponding second feature of the set of initial features.

[0146] Example 3 provides the method according to Example 2, where the second overlay error is different from the third overlay error.

[0147] Example 4 provides the method according to Examples 2 or 3, where the first overlay error is different from the second overlay error.

[0148] Example 5 provides the method according to any one of Examples 1-4, where the set of maskless features are formed in a layer above the first layer.

[0149] Example 6 provides the method according to any one of Examples 1-4, where the set of maskless features are formed in a layer below the first layer. [0150] Example 7 provides the method according to any one of Examples 1-4, where the set of maskless features are formed in the first layer.

[0151] Example 8 provides the method according to any one of Examples 1-7, where the set of mask-based features includes a plurality of first openings and the set of maskless features includes a plurality of second openings, and where the plurality of second openings have dimensions smaller than dimensions of the plurality of first openings. A further Example provides the method according to Example 8, further including filling the plurality of first openings and the plurality of second openings with one or more electrically conductive materials.

[0152] Example 9 provides the method according to any one of Examples 1-7, where forming the set of maskless features includes adjusting dimensions of one or more features of the set of mask- based features.

[0153] Example 10 provides the method according to Example 1, where forming the set of maskless features includes eliminating one or more of the set of mask-based features.

[0154] Example 11 provides the method according to any one of Examples 1-10, where the mask- based lithographic process includes photolithography and where the maskless lithographic process includes electron beam lithography.

[0155] In the method according to any one of the preceding Examples, the electrically conductive material may include one or more of aluminum, copper, tungsten, cobalt, ruthenium, nickel, iron, and molybdenum, and/or one or more alloys including aluminum, copper, tungsten, cobalt, ruthenium, manganese, magnesium, boron, phosphorus, nitrogen, carbon, and sulfur.

[0156] In the method according to any one of the preceding Examples, the electrically conductive elements may be interconnects of the semiconductor device.

[0157] Example 12 provides a metallization stack for providing electrical connectivity, including a plurality of initial features provided in a first layer of an interconnect support layer; a plurality of mask-based features provided in a second layer of the interconnect support layer, the second layer disposed over the first layer; and a plurality of maskless features provided in a third layer of the interconnect support layer. Each feature of the plurality of mask-based features at least partially overlaps a corresponding feature of the plurality of initial features and has a first overlay error with respect to the corresponding feature of the plurality of initial features and a first feature of the plurality of maskless features has a second overlay error, different from the first overlay error, with respect to a corresponding first feature of the plurality of initial features, the corresponding first feature of the plurality of initial features also having a corresponding first feature of the plurality of mask-based features. Thus, an overlay error of a maskless feature with respect to a corresponding feature of the plurality of initial features is different than an overlay error of a mask-based feature corresponding to the same one of the initial features.

[0158] Example 13 provides the metallization stack according to Example 12, where a second feature of the plurality of maskless features has a third overlay error, different from the second overlay error, with respect to a corresponding second feature of the plurality of initial features, the corresponding second feature of the plurality of initial features also having a corresponding second feature of the plurality of mask-based features. Thus, not only may overlay errors of maskless features with respect to corresponding features of the plurality of initial features be different than overlay errors of mask-based features corresponding to the same initial features, but overlay errors of different maskless features may be different from one another, making maskless features clearly distinguishable from mask-based features.

[0159] Example 14 provides the metallization stack according to Examples 12 or 13, where the third layer is disposed over the second layer.

[0160] Example 15 provides the metallization stack according to Examples 12 or 13, where the third layer is disposed between the first layer and the second layer.

[0161] Example 16 provides the metallization stack according to any one of Examples 12-15, where the plurality of mask-based features and the plurality of maskless features include a plurality of openings filled with one or more electrically conductive materials.

[0162] Example 17 provides the metallization stack according to Example 16, the one or more electrically conductive materials include one or more of aluminum, copper, tungsten, cobalt, ruthenium, nickel, iron, and molybdenum, and/or one or more alloys including aluminum, copper, tungsten, cobalt, ruthenium, manganese, magnesium, boron, phosphorus, nitrogen, carbon, and sulfur.

[0163] Example 18 provides the metallization stack according to any one of Examples 12-17, where the plurality of mask-based features are formed using mask-based lithography and the plurality of maskless features are formed using maskless lithography.

[0164] Example 19 provides an integrated circuit package, including a component and a metallization stack for providing electrical connectivity to the component. The metallization stack includes a plurality of initial features provided in a first layer of an interconnect support layer; a plurality of mask-based features provided in a second layer of the interconnect support layer, the second layer disposed over the first layer; a plurality of maskless features provided in a third layer of the interconnect support layer, where each feature of the plurality of mask-based features at least partially overlaps a corresponding feature of the plurality of initial features and has a first overlay error with respect to the corresponding feature of the plurality of initial features, and a first feature of the plurality of maskless features has a second overlay error, different from the first overlay error, with respect to a corresponding first feature of the plurality of initial features, the corresponding first feature of the plurality of initial features also having a corresponding first feature of the plurality of mask-based features.

[0165] Example 20 provides the integrated circuit package according to Example 19, where the component includes a transistor, a die, a sensor, a processing device, or a memory device.

[0166] Example 21 provides a computing device that may include a substrate and an integrated circuit (IC) die coupled to the substrate. The IC die may include a semiconductor device having a component, and a metallization stack for providing electrical connectivity to the component. The metallization stack may include a plurality of initial features provided in a first layer of an interconnect support layer; a plurality of mask-based features provided in a second layer of the interconnect support layer, the second layer disposed over the first layer; and a plurality of maskless features provided in a third layer of the interconnect support layer, where each feature of the plurality of mask-based features at least partially overlaps a corresponding feature of the plurality of initial features and has a first overlay error with respect to the corresponding feature of the plurality of initial features, and a first feature of the plurality of maskless features has a second overlay error, different from the first overlay error, with respect to a corresponding first feature of the plurality of initial features, the corresponding first feature of the plurality of initial features also having a corresponding first feature of the plurality of mask-based features.

[0167] Example 22 provides the computing device according to Example 21, where a second feature of the plurality of maskless features has a third overlay error, different from the second overlay error, with respect to a corresponding second feature of the plurality of initial features, the corresponding second feature of the plurality of initial features also having a corresponding second feature of the plurality of mask-based features.

[0168] Example 23 provides the computing device according to Example 21, where the computing device is a wearable or handheld computing device.

[0169] Example 24 provides the computing device according to any of Examples 21-23, where the computing device further includes one or more communication chips and an antenna.

[0170] Example 25 provides the computing device according to any of Examples 21-23, where the substrate is a motherboard.

[0171] The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize.

[0172] These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following Examples should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims. Rather, the scope of the disclosure is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.