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Title:
METHODS FOR DAMAGE ETCH AND TEXTURING OF SILICON SINGLE CRYSTAL SUBSTRATES
Document Type and Number:
WIPO Patent Application WO/2010/090922
Kind Code:
A1
Abstract:
Methods for performing damage etch and texturing of single crystal silicon substrates, particularly for use as solar cells or photovoltaic cells. Damage etch with a TMAH solution followed by texturing using solution of KOH or NaOH mixed with IPA is particularly advantageous. The substitution of some of the IPA with ethylene glycol further improves results. Also disclosed is a process that combines both damage etch and texturing etch into a single step.

Inventors:
DOVE CURTIS (US)
DUTTON CINDY (US)
BAUER GREG (US)
MYERS CHRISTOPHER (US)
BALOOCH MEHDI (US)
Application Number:
PCT/US2010/022214
Publication Date:
August 12, 2010
Filing Date:
January 27, 2010
Export Citation:
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Assignee:
ASIA UNION ELECTRONIC CHEMICAL
DOVE CURTIS (US)
DUTTON CINDY (US)
BAUER GREG (US)
MYERS CHRISTOPHER (US)
BALOOCH MEHDI (US)
International Classes:
H01L21/02; H01L21/302; H01L21/461
Foreign References:
US20080160661A12008-07-03
US20070278183A12007-12-06
US6451218B12002-09-17
US20080004197A12008-01-03
US20070072423A12007-03-29
Attorney, Agent or Firm:
HEY, David, A. (575 Mountain AvenueMurray Hill, NJ, US)
Download PDF:
Claims:
CLAIMS

What is claimed:

1. A method of removing damage from a single crystal silicon surface comprising: treating the single crystal silicon surface with a tetramethylammonium hydroxide solution.

2. The method of claim 1 wherein the damage is caused by saw cutting.

3. The method of claim 1 wherein the silicon surface is the surface of a single crystal silicon wafer for use in a photovoltaic or solar cell device.

4. The method of claim 1 wherein in the silicon surface is the surface of a single crystal silicon wafer for use in a MEMS or integrated circuit device.

5. The method of claim 1 wherein treating comprises etching.

6. A method of forming a semiconductor device comprising: providing a single crystal silicon wafer having damage on a surface thereof; treating the wafer with a tetramethylammonium hydroxide solution to remove the damage; and treating the wafer with a texturing solution to form pyramidal structures on the wafer.

7. A method of claim 6 wherein the damage is caused by saw cutting.

8. The method of claim 6 wherein the semiconductor device is a photovoltaic or solar cell device.

9. The method of claim 6 wherein the semiconductor device is a MEMS or integrated circuit device

10. The method of claim 6 wherein treating with the tetramethylammonium hydroxide solution comprises etching.

11. The method of claim 6 wherein the texturing solution comprises potassium hydroxide or sodium hydroxide and isopropyl alcohol.

12. The method of claim 11 wherein the ratio of potassium hydroxide or sodium hydroxide to isopropyl alcohol in the texturing solution is varied during treatment of the wafer with the texturing solution.

13. The method of claim 6 wherein the texturing solution comprises potassium hydroxide or sodium hydroxide, isopropyl alcohol and ethylene glycol.

14. The method of claim 13 wherein the ratio of potassium hydroxide or sodium hydroxide to isopropyl alcohol to ethylene glycol in the texturing solution is varied during treatment of the wafer with the texturing solution.

15. A method of forming a semiconductor device comprising: providing a single crystal silicon wafer having damage on a surface thereof; treating the wafer with a solution comprising a fluorinated compound and an alkaline solution to simultaneously remove the damage and to texture the surface of the wafer.

16. The method of claim 15 wherein the fluorinated compound is ammonium fluoride or ammonium bifluoride.

17. The method of claim 15 wherein the alkaline solution is tetramethyl ammonium hydroxide.

18. The method of claim 15 wherein the fluorinated compound is ammonium fluoride, the alkaline solution is tetramethylammonium and the solution comprises a ratio of tetramethylammonium to ammonium fluoride in the range of 4 to 4.5.

19. The method of claim 15 wherein treating the wafer is carried out at temperatures of 1000C or less.

20. The method of claim 15 wherein the solution further includes additives.

2 L The method of claim 20 wherein the additives are isopropyl alcohol, ethylene glycol or a combination thereof.

22. The method of claim 20 wherein the additive is potassium hydroxide or sodium hydroxide.

23. A method of claim 15 wherein the damage is caused by saw cutting.

24. The method of claim 15 wherein the semiconductor device is a photovoltaic or solar cell device.

25. The method of claim 15 wherein the semiconductor device is a MEMS or integrated circuit device.

26. The method of claim 15 wherein the ratio of fluorinated compound to alkaline solution is varied during treatment of the wafer with the solution.

Description:
METHODS FOR DAMAGE ETCH AND TEXTURING QF SILICON SINGLE

CRYSTAL SUBSTRATES

FIELD OF THE INVENTION

(001) The present invention relates to methods of performing damage etch and texturing of single crystal silicon substrates, particularly for use as solar cells or photovoltaic cells.

BACKGROUND OF THE INVENTION

(002) Photovoltaic solar cells are thin silicon disks that can be used to convert sunlight into electricity and serve as an energy source for a wide variety of uses. For example, small area solar cells can be used to power calculators, cell phones and other small electronic devices. Larger panels can be used for supplementing or fulfilling the electrical needs of individual residences, lights, pumping, cooling, heating, etc.

(003) Research into the use of solar energy as a power source began as early as 1839 with the discovery that materials that were sensitive to light could be used to convert sunlight into electricity. An early solar cell, made of gold-coated selenium was produced in 1877, although it was only one percent efficient, i.e. converted only one percent of the incoming sunlight into electricity. Einstein's explanation of the photoelectric effect in 1905 spurred new interest in producing solar electricity at higher efficiencies. However, little progress was made until advances in diodes and transistors allowed silicon solar cells exhibiting four percent efficiency to be produced in 1954. Further work produced solar cells having efficiency up to 15 percent that were used in rural and isolated areas as power sources for a telephone relay system.

(004) In order to meet domestic energy needs, efficiency of solar cells had to be further improved, while maintaining cost effectiveness. Conventional silicon based high efficiency solar cells are produced from single crystalline silicon. In order to make single crystalline silicon wafers, pure silicon starting material must first be obtained. Pure silicon is produced from silicon dioxide of either quartzite gravel or crushed quartz that has been processed in an electric arc furnace to release oxygen and produce carbon dioxide and molten silicon. While this process yields silicon with only one percent impurities, the solar cell industry requires higher purity. One way to produce high purity silicon is to further process the 99 percent pure silicon using a floating zone technique wherein a rod of silicon is passed through a heated zone several times in the same direction. This procedure acts to drag the impurities toward one end of the silicon rod. Once the silicon reaches the desired purity level, the end containing the impurities is removed.

(005) Another method for producing high purity single crystalline wafers is known as the Czochralski method. In this process, a boule of silicon is created, by repeatedly dipping a seed crystal of silicon into melted silicon. As the seed crystal is withdrawn and rotated, a cylindrical ingot, the boule, of single crystalline silicon is formed. This boule is highly pure because impurities tend to remain in the liquid silicon.

(006) Silicon wafers are sliced from the boule one at a time using a single blade circular saw or many at time using a multiwire saw. Slicing results in loss of up to half of the original boule and further cutting may be carried out to shape the wafers into rectangles or hexagons, for fitting together into a solar cell array. The slicing and cutting of the wafers creates roughness and defects caused by saw-damage. These areas of roughness and damage must be removed in order to form an abrupt, defect free p-n junction and contact wires needed for the final solar cell. Roughness and damage is typically removed by an aggressive anisotropic etch process known as "damage etch".

(007) Several different etch solutions have been proposed and used to perform the damage etch. The most common technique for single crystals uses an etching solution of KOH or NaOH solutions in deionized (DI) water at about 80 0 C. However, the use of these etching solutions exhibit significant disadvantages. In particular, KOH or NaOH solutions do not wet the silicon surface well, and frequently experience non-uniform hydrogen bubble buildup that prevents uniform contact between the silicon surface and the etching solution. This can result in non-uniform etching across the wafer, which leads to variation in solar cell efficiency and lower reproducibility of the solar cell product. In addition, the KOH or NaOH solutions do not efficiently or effectively remove contaminants that are caused by the saw slicing and do not passivate the surface of the silicon, again resulting in a reduction in the efficiency of the solar cells produced.

(008) Other solutions have been used to etch silicon, but have not been suggested for use in solar cell damage etch processes. Rather, tetramethylammonium hydroxide (TMAH), isopropyl alcohol (IPA) and pyrazine have been used to etch silicon for use in MEMS applications. These solutions provide an etch that obtains a flat surface with minimal undercutting of mask layers, (see Chung, Anisotropic Etching Characteristics of Si in Tetramethylammonium Hydroxide : Isopropyl Alchohol : Pyrazine Solutions, Journal of the Korean Physical Society, Vol. 46, No. 5, May 2005, pp. 1152-1156).\

(009) The result of the damage etch process is a silicon wafer that is very shiny and reflective. The efficiency of a solar cell is determined by the ability to gather or absorb light. While silicon has a large absorption coefficient in the visible light spectrum, it also exhibits a high reflection coefficient. To increase efficiency of solar cells, the reflectivity of the damage etched silicon wafer must be reduced. One common method of reducing reflectance is to coat the silicon wafer with an anti -reflective coating (ARC), such as silicon oxide, silicon nitride or titanium dioxide. However, these films exhibit resonance structures that limit their effectiveness to a small range of angles and wavelengths, such that efficiency depends on the angle of incidence of the light. (010) Another method of reducing reflectance and improving solar cell efficiency is to texture the silicon wafer surface using a wet-chemical etch to from pyramidal structures. These structures provide higher levels of light trapping based on geometrical optics, e.g. the texturing is on a scale equal to or greater than optical wavelengths of the incident light causing the incident light to reflect multiple times and thereby enhance absorption.

(011) The texturing process is generally carried out using a mixture of KOH or NaOH and IPA in DI water as the etchant. (See US Pat. No. 3,998,659; Gangopadhyah et al, A novel low cost texturization method for large area commercial mono-crystalline silicon solar cells, Solar Energy Materials & Solar Cells, 90, 2006, pp. 3557-3567; King et al., Proceedings of 22 nd IEEE International Photovoltaic Specialists Conference, Las Vegas, 1991, pp. 303-308). The addition of IPA serves to mask specific silicon sites, preventing etching by the solution, to thereby form the pyramidal structures. It has also been reported that a combination of IPA and aqueous alkaline ethylene glycol resulted in more uniform pyramidal texturing on highly polished silicon (100) for use in semiconductor electronic applications. (See US Pat. No. 6,451,218). In addition, the use of sodium acetate, anhydrous (CH 3 COONa) operates in a similar manner to IPA for alkaline texturing, however the two compounds can not co-exist, (see Zhenqiang Xi et al, Investigation of texturization for monocrystalline silicon solar cells with different kinds of alkaline, Renewable Energy 29, 2004, pp. 2101-2107). In none of the references noted above has the use of the solutions mentioned been applied to as-cut silicon wafers for purposes texturing a sample that still has saw damage and contamination.

(012) As noted above, the diluted KOH or NaOH damage etch solutions have poor silicon wetability characteristics and do not remove surface contamination effectively, leading to reduced solar cell efficiency and reproducibility. (013) There remains a need in the art for improvements to the efficiency of solar cells and to methods of performing damage etch and texturing of single crystal silicon substrates.

SUMMARY OF THE PRESENT INVENTION

(014) The present invention provides improved methods for performing damage etch and texturing of single crystal silicon substrates, particularly for use as solar cells or photovoltaic cells. In particular, the present invention performs damage etching with a TMAH solution followed by texturing using a KOH and IPA solution. A further embodiment comprises substitution of a portion of the IPA with ethylene glycol (EG). In addition, the present invention provides for a process that combines both damage etch and texturing etch into a single step.

BRIEF DESCRIPTION OF THE DRAWINGS

(015) Figure 1 is an atomic force microscopy (AFM) view of the surface of an as-cut single crystalline silicon wafer.

(016) Figure 2 is an AFM view of the surface of a single crystalline silicon wafer following damage etch using a TMAH etch solution according to one embodiment of the present invention.

(017) Figure 3 is an AFM view of a single crystalline silicon wafer following texturing of the surface in accordance with a further embodiment of the present invention.

(018) Figure 4 is a graph showing reflectance values for the silicon wafer at different stages of the process according to the present invention. (019) Figure 5 shows optical images and associated etch depth graphs showing the results of a single step process using different TMAH to NH 4 F ratio solutions according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

(020) The present invention sets forth improved methods for carrying out damage etch and texturing of single crystal silicon substrates. These silicon substrates are particularly useful as solar cells or photovoltaic cells.

(021) In one embodiment of the present invention a TMAH solution is used to perform damage etch of an as-cut single crystalline wafer. Texturing of the wafer surface is then done with a solution comprising KOH or NaOH mixed with IPA. TMAH provides good wetting of the silicon wafer surface, unlike the KOH or NaOH solutions used in the prior art. Therefore, using TMAH as the damage etch solution produces a stronger, more resilient wafer that is better prepared to withstand the texturing etch process. After the damage etch is competed, texturing is carried out with a KOH or NaOH mixed with IPA solution that provides uniform pyramidal structures having very low reflectance values.

(022) In a further embodiment of the present invention, by replacing a portion, preferably at least half, of the IPA in the texturing solution with ethylene glycol, even better wetting of the silicon surface is achieved. By including ethylene glycol in the mixture, even lower reflectance values can be achieved and the solution is less expensive and less volatile. This is at least in part because IPA has a very low boiling point and is lost through evaporation during the process. The combination of a TMAH solution for damage etch followed by a KOH or NaOH, IPA and ethylene glycol solution for texturing, also has the advantages that less hazardous waste is produced, greater duration of use for the solutions in situ is possible and surface topography, morphology and uniformity is optimized. Moreover, solar cells produced using the etch solutions according to the present invention, exhibit lower reflectance of light from the UV to the IR range.

(023) The embodiments above each describe a two step process, i.e. separate damage etch and texturing processes. According to a further embodiment of the present invention, a process that combines both damage etch and texturing into a single step is possible. By using a mixture of a fluorinated compound and an alkaline solution it is possible to remove as-cut damage and imbedded impurities, smooth the wafer surface on a macro-scale and perform texturing on a micro-scale in a single step process. In particular, a mixture of ammonium fluoride (NH 4 F) or ammonium bifiuoride (NH4HF2) and TMAH may be used in a single step process at temperatures up to 100 0 C according to the present invention. Additives may be included in the mixture to improve wetting capability and etch rate. The addition of such additives, assists in the formation of pyramidal structures, effectively removes contaminants and passivates the wafer surface thus helping to improve efficiency of solar cell product. Passivation occurs by hydrogen atoms filling the existing silicon dangling that exist on the surface of the silicon wafer. Additives such as IPA and ethylene glycol can be included to improve the wetting capability. In one embodiment of the present invention, a mixture of ammonium fluoride (NH 4 F) or ammonium bifiuoride (NH 4 HF 2 ), KOH or NaOH, and TMAH may be used in the single step process according to the present invention.

(024) A further refinement of the present invention can be carried out by modifying the solutions during processing, hi particular, as wafers are etched, the etching solution chemical characteristics can change because of the dissolution of silicon into the bath, hi order to maintain etch rates at an optimum rate, the etch solution can be modified to compensate for this chemical change. This modification can be carried out in any of the embodiments of the present invention, i.e. two step process or single step process. (025) By performing the damage etch and texturing according to the present invention, several advantages are achieved. In particular, the chemicals used are more environmentally friendly and a lower quantity is required. In addition, these chemicals are less dangerous to work with than those used in the prior art processes. Moreover, the methods of the present invention result in high efficiency solar cells that can be reproduced with greater uniformity.

(026) Some results achieved by using the present invention are shown in Figures 1 through 4. In particular, Figure 1 is an atomic force microscopy (AFM) view of the surface of an as-cut single crystalline silicon wafer showing macro-roughness troughs 10- 20 μm in height as well as local micro -roughness of less than a micron. As noted above, this roughness as well as contaminants, e.g. abraded metal from the saw wire and grinding abrasive, must be removed for the wafer to be useful as a solar cell. According to one embodiment of the present invention, the silicon surface is smoothed and contaminants removed by using a TMAH etch solution. Figure 2 is an AFM view of the surface of a single crystalline silicon wafer following damage etch using a TMAH etch solution according to the present invention. As can be seen in Figure 2, the TMAH damage etch was successful in completely removing micro-roughness and reduced macro-roughness to less than a micron. In addition, most of the abraded contaminants were removed. The result is a very uniform and smooth surface. Texturing is then carried out using a KOH and IPA solution. Figure 3 is an AFM view of a single crystalline silicon wafer following the texturing of the surface in accordance with the present invention and shows extremely uniform pyramidal formations across the wafer. Reflectance values for the silicon wafer at different stages of the present invention are shown in Figure 4. In particular, a silicon wafer following damage etch with TMAH shows a relatively high degree of reflectance, 35 to 40 percent, in the visible light range. This reflectance is reduced to about 20% in the visible light range following the texturing step when using a KOH and IPA solution. Lower reflectance values, i.e. less than 8% in the visible light range, are achieved when about half of the IPA is replaced with ethylene glycol, while maintaining overall uniformity.

(027) Figure 5 shows optical images and associated etch depth graphs of the results of a single step process according to an embodiment of the present invention. In particular, Figure 5 shows various results from the use of a combined mixture of TMAH and NH 4 F in a single step process of performing both damage etch and texturing. The graph shows the ratio of TMAH to NH 4 F plotted against the damage etch in μm. While high ratios of TMAH to NH 4 F provide high etch rates, surface roughness of the silicon wafer is reduced to the point that higher, unacceptable reflectance is exhibited. This can be seen from the optical images C, D, E. Low ratios of TMAH to NH 4 F leave the desired small pyramidal density and corresponding reduction of reflectance, but the etch rate for removing damage is also small, as can be seen in the optical image A and the graph. An optimum ratio of TMAH to NH 4 F is obtained in the range of 4 to 4.5 where the damage etch is high and a high density of pyramids is also formed (black spots) as seen in optical image B. The optimum ratio of TMAH to ammonium fluoride or ammonium di-fiuoride may also depend on the amount of silicon dissolved into the solutions. Therefore, the present invention contemplates modification of the solution ratio as the process takes place, hi addition, the etch rate can be further accelerated by adding KOH or NaOH to the mixture of TMAH and fluorides. The addition of KOH or NaOH is particularly favorable for industrial purposes as it may allow reductions of cost.

(028) While the present invention has been described particularly with respect to the production of solar cells, similar methods will be useful in other device production, such as MEMS and semiconductor processing for integrated circuits. It is anticipated that other embodiments and variations of the present invention will become readily apparent to the skilled artisan in the light of the foregoing description, and it is intended that such embodiments and variations likewise be included within the scope of the invention as set out in the appended claims.